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fix build 2.0

vulkanasync
CamilleLaVey 1 month ago
parent
53dd313ee5
commit
769a4c043a
1 changed files with 9 additions and 9 deletions
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  1. 18
      src/video_core/renderer_vulkan/vk_rasterizer.cpp

18
src/video_core/renderer_vulkan/vk_rasterizer.cpp
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@ -1493,12 +1493,12 @@ void RasterizerVulkan::UpdateStencilFaces(Tegra::Engines::Maxwell3D::Regs& regs,
return; return;
} }
} }
if (cmdbuf) {
if (cmd) {
const bool set_back = regs.stencil_two_side_enable && regs.stencil_front_ref != regs.stencil_back_ref; const bool set_back = regs.stencil_two_side_enable && regs.stencil_front_ref != regs.stencil_back_ref;
cmdbuf->SetStencilReference(set_back ? VK_STENCIL_FACE_FRONT_BIT : VK_STENCIL_FACE_FRONT_AND_BACK,
cmd->SetStencilReference(set_back ? VK_STENCIL_FACE_FRONT_BIT : VK_STENCIL_FACE_FRONT_AND_BACK,
regs.stencil_front_ref); regs.stencil_front_ref);
if (set_back) { if (set_back) {
cmdbuf->SetStencilReference(VK_STENCIL_FACE_BACK_BIT, regs.stencil_back_ref);
cmd->SetStencilReference(VK_STENCIL_FACE_BACK_BIT, regs.stencil_back_ref);
} }
} else { } else {
scheduler.Record([front_ref = regs.stencil_front_ref, back_ref = regs.stencil_back_ref, scheduler.Record([front_ref = regs.stencil_front_ref, back_ref = regs.stencil_back_ref,
@ -1526,12 +1526,12 @@ void RasterizerVulkan::UpdateStencilFaces(Tegra::Engines::Maxwell3D::Regs& regs,
return; return;
} }
} }
if (cmdbuf) {
if (cmd) {
const bool set_back = regs.stencil_two_side_enable && regs.stencil_front_mask != regs.stencil_back_mask; const bool set_back = regs.stencil_two_side_enable && regs.stencil_front_mask != regs.stencil_back_mask;
cmdbuf->SetStencilWriteMask(set_back ? VK_STENCIL_FACE_FRONT_BIT : VK_STENCIL_FACE_FRONT_AND_BACK,
cmd->SetStencilWriteMask(set_back ? VK_STENCIL_FACE_FRONT_BIT : VK_STENCIL_FACE_FRONT_AND_BACK,
regs.stencil_front_mask); regs.stencil_front_mask);
if (set_back) { if (set_back) {
cmdbuf->SetStencilWriteMask(VK_STENCIL_FACE_BACK_BIT, regs.stencil_back_mask);
cmd->SetStencilWriteMask(VK_STENCIL_FACE_BACK_BIT, regs.stencil_back_mask);
} }
} else { } else {
scheduler.Record([front_write_mask = regs.stencil_front_mask, scheduler.Record([front_write_mask = regs.stencil_front_mask,
@ -1560,12 +1560,12 @@ void RasterizerVulkan::UpdateStencilFaces(Tegra::Engines::Maxwell3D::Regs& regs,
return; return;
} }
} }
if (cmdbuf) {
if (cmd) {
const bool set_back = regs.stencil_two_side_enable && regs.stencil_front_func_mask != regs.stencil_back_func_mask; const bool set_back = regs.stencil_two_side_enable && regs.stencil_front_func_mask != regs.stencil_back_func_mask;
cmdbuf->SetStencilCompareMask(set_back ? VK_STENCIL_FACE_FRONT_BIT : VK_STENCIL_FACE_FRONT_AND_BACK,
cmd->SetStencilCompareMask(set_back ? VK_STENCIL_FACE_FRONT_BIT : VK_STENCIL_FACE_FRONT_AND_BACK,
regs.stencil_front_func_mask); regs.stencil_front_func_mask);
if (set_back) { if (set_back) {
cmdbuf->SetStencilCompareMask(VK_STENCIL_FACE_BACK_BIT, regs.stencil_back_func_mask);
cmd->SetStencilCompareMask(VK_STENCIL_FACE_BACK_BIT, regs.stencil_back_func_mask);
} }
} else { } else {
scheduler.Record([front_test_mask = regs.stencil_front_func_mask, scheduler.Record([front_test_mask = regs.stencil_front_func_mask,

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