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@ -288,6 +288,19 @@ union Instruction { |
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} |
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} |
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} texs; |
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} texs; |
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union { |
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BitField<20, 5, u64> target; |
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BitField<5, 1, u64> constant_buffer; |
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s32 GetBranchTarget() const { |
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// Sign extend the branch target offset |
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u32 mask = 1U << (5 - 1); |
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u32 value = static_cast<u32>(target); |
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// The branch offset is relative to the next instruction, so add 1 to it. |
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return static_cast<s32>((value ^ mask) - mask) + 1; |
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} |
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} bra; |
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BitField<61, 1, u64> is_b_imm; |
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BitField<61, 1, u64> is_b_imm; |
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BitField<60, 1, u64> is_b_gpr; |
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BitField<60, 1, u64> is_b_gpr; |
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BitField<59, 1, u64> is_c_gpr; |
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BitField<59, 1, u64> is_c_gpr; |
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@ -306,6 +319,7 @@ class OpCode { |
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public: |
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public: |
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enum class Id { |
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enum class Id { |
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KIL, |
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KIL, |
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BRA, |
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LD_A, |
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LD_A, |
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ST_A, |
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ST_A, |
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TEX, |
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TEX, |
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@ -470,6 +484,7 @@ private: |
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std::vector<Matcher> table = { |
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std::vector<Matcher> table = { |
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#define INST(bitstring, op, type, name) Detail::GetMatcher(bitstring, op, type, name) |
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#define INST(bitstring, op, type, name) Detail::GetMatcher(bitstring, op, type, name) |
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INST("111000110011----", Id::KIL, Type::Flow, "KIL"), |
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INST("111000110011----", Id::KIL, Type::Flow, "KIL"), |
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INST("111000100100----", Id::BRA, Type::Flow, "BRA"), |
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INST("1110111111011---", Id::LD_A, Type::Memory, "LD_A"), |
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INST("1110111111011---", Id::LD_A, Type::Memory, "LD_A"), |
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INST("1110111111110---", Id::ST_A, Type::Memory, "ST_A"), |
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INST("1110111111110---", Id::ST_A, Type::Memory, "ST_A"), |
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INST("1100000000111---", Id::TEX, Type::Memory, "TEX"), |
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INST("1100000000111---", Id::TEX, Type::Memory, "TEX"), |
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