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fix %rbp

lizzie/regalloc-exclude-rbp
lizzie 1 week ago
parent
commit
6f90dddb49
  1. 9
      src/dynarmic/src/dynarmic/backend/x64/a32_emit_x64.cpp
  2. 17
      src/dynarmic/src/dynarmic/backend/x64/a64_emit_x64.cpp
  3. 5
      src/dynarmic/src/dynarmic/backend/x64/stack_layout.h

9
src/dynarmic/src/dynarmic/backend/x64/a32_emit_x64.cpp

@ -114,6 +114,8 @@ A32EmitX64::BlockDescriptor A32EmitX64::Emit(IR::Block& block) {
// Start emitting.
code.align();
const u8* const entrypoint = code.getCurr();
code.mov(code.qword[rsp + ABI_SHADOW_SPACE + offsetof(StackLayout, abi_base_pointer)], rbp);
code.lea(rbp, code.ptr[rsp + ABI_SHADOW_SPACE + offsetof(StackLayout, abi_base_pointer) - 8]);
EmitCondPrelude(ctx);
@ -146,15 +148,14 @@ A32EmitX64::BlockDescriptor A32EmitX64::Emit(IR::Block& block) {
reg_alloc.AssertNoMoreUses();
if (conf.enable_cycle_counting) {
if (conf.enable_cycle_counting)
EmitAddCycles(block.CycleCount());
}
code.mov(rbp, code.qword[rsp + ABI_SHADOW_SPACE + offsetof(StackLayout, abi_base_pointer)]);
EmitTerminal(block.GetTerminal(), ctx.Location().SetSingleStepping(false), ctx.IsSingleStep());
code.int3();
for (auto& deferred_emit : ctx.deferred_emits) {
for (auto& deferred_emit : ctx.deferred_emits)
deferred_emit();
}
code.int3();
const size_t size = size_t(code.getCurr() - entrypoint);

17
src/dynarmic/src/dynarmic/backend/x64/a64_emit_x64.cpp

@ -88,9 +88,8 @@ A64EmitX64::BlockDescriptor A64EmitX64::Emit(IR::Block& block) noexcept {
// Start emitting.
code.align();
const auto* const entrypoint = code.getCurr();
// code.mov(code.qword[rsp + ABI_SHADOW_SPACE + offsetof(StackLayout, abi_base_pointer)], rbp);
// code.lea(rbp, code.ptr[rsp + ABI_SHADOW_SPACE - 8]);
code.mov(code.qword[rsp + ABI_SHADOW_SPACE + offsetof(StackLayout, abi_base_pointer)], rbp);
code.lea(rbp, code.ptr[rsp + ABI_SHADOW_SPACE + offsetof(StackLayout, abi_base_pointer) - 8]);
DEBUG_ASSERT(block.GetCondition() == IR::Cond::AL);
typedef void (EmitX64::*EmitHandlerFn)(EmitContext& context, IR::Inst* inst);
@ -142,19 +141,13 @@ finish_this_inst:
}
reg_alloc.AssertNoMoreUses();
if (conf.enable_cycle_counting) {
if (conf.enable_cycle_counting)
EmitAddCycles(block.CycleCount());
}
//code.mov(rbp, code.qword[rsp + ABI_SHADOW_SPACE + offsetof(StackLayout, abi_base_pointer)]);
code.mov(rbp, code.qword[rsp + ABI_SHADOW_SPACE + offsetof(StackLayout, abi_base_pointer)]);
EmitTerminal(block.GetTerminal(), ctx.Location().SetSingleStepping(false), ctx.IsSingleStep());
code.int3();
for (auto& deferred_emit : ctx.deferred_emits) {
for (auto& deferred_emit : ctx.deferred_emits)
deferred_emit();
}
code.int3();
const size_t size = size_t(code.getCurr() - entrypoint);

5
src/dynarmic/src/dynarmic/backend/x64/stack_layout.h

@ -22,12 +22,13 @@ constexpr size_t SpillCount = 64;
#endif
struct alignas(16) StackLayout {
u64 abi_base_pointer;
// Needs alignment for VMOV and XMM spills
alignas(16) std::array<std::array<u64, 2>, SpillCount> spill;
s64 cycles_remaining;
s64 cycles_to_run;
std::array<std::array<u64, 2>, SpillCount> spill;
u32 save_host_MXCSR;
bool check_bit;
u64 abi_base_pointer;
};
#ifdef _MSC_VER

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