ReinUsesLisp
5 years ago
committed by
ameerj
ameerj
32 changed files with 479 additions and 285 deletions
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2src/shader_recompiler/CMakeLists.txt
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29src/shader_recompiler/backend/spirv/emit_context.cpp
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6src/shader_recompiler/backend/spirv/emit_context.h
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2src/shader_recompiler/backend/spirv/emit_spirv.cpp
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103src/shader_recompiler/backend/spirv/emit_spirv.h
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28src/shader_recompiler/backend/spirv/emit_spirv_bitwise_conversion.cpp
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48src/shader_recompiler/backend/spirv/emit_spirv_composite.cpp
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2src/shader_recompiler/backend/spirv/emit_spirv_control_flow.cpp
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89src/shader_recompiler/backend/spirv/emit_spirv_convert.cpp
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48src/shader_recompiler/backend/spirv/emit_spirv_floating_point.cpp
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16src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
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72src/shader_recompiler/backend/spirv/emit_spirv_logical.cpp
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22src/shader_recompiler/backend/spirv/emit_spirv_memory.cpp
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2src/shader_recompiler/frontend/ir/condition.h
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70src/shader_recompiler/frontend/ir/ir_emitter.cpp
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4src/shader_recompiler/frontend/ir/microinstruction.cpp
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2src/shader_recompiler/frontend/ir/microinstruction.h
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6src/shader_recompiler/frontend/ir/opcodes.inc
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2src/shader_recompiler/frontend/ir/program.cpp
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2src/shader_recompiler/frontend/maxwell/program.cpp
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62src/shader_recompiler/frontend/maxwell/translate/impl/floating_point_conversion_integer.cpp
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2src/shader_recompiler/frontend/maxwell/translate/impl/impl.h
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18src/shader_recompiler/ir_opt/collect_shader_info_pass.cpp
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12src/shader_recompiler/ir_opt/constant_propagation_pass.cpp
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79src/shader_recompiler/ir_opt/lower_fp16_to_fp32.cpp
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1src/shader_recompiler/ir_opt/passes.h
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10src/shader_recompiler/main.cpp
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2src/shader_recompiler/object_pool.h
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3src/video_core/renderer_vulkan/vk_compute_pass.cpp
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8src/video_core/renderer_vulkan/vk_pipeline_cache.cpp
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2src/video_core/renderer_vulkan/vk_rasterizer.cpp
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10src/video_core/vulkan_common/vulkan_device.cpp
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "shader_recompiler/backend/spirv/emit_spirv.h"
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namespace Shader::Backend::SPIRV { |
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Id EmitConvertS16F16(EmitContext& ctx, Id value) { |
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return ctx.OpUConvert(ctx.U32[1], ctx.OpConvertFToS(ctx.U16, value)); |
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} |
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Id EmitConvertS16F32(EmitContext& ctx, Id value) { |
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return ctx.OpUConvert(ctx.U32[1], ctx.OpConvertFToS(ctx.U16, value)); |
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} |
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Id EmitConvertS16F64(EmitContext& ctx, Id value) { |
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return ctx.OpUConvert(ctx.U32[1], ctx.OpConvertFToS(ctx.U16, value)); |
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} |
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Id EmitConvertS32F16(EmitContext& ctx, Id value) { |
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return ctx.OpConvertFToS(ctx.U32[1], value); |
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} |
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Id EmitConvertS32F32(EmitContext& ctx, Id value) { |
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return ctx.OpConvertFToS(ctx.U32[1], value); |
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} |
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Id EmitConvertS32F64(EmitContext& ctx, Id value) { |
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return ctx.OpConvertFToS(ctx.U32[1], value); |
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} |
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Id EmitConvertS64F16(EmitContext& ctx, Id value) { |
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return ctx.OpConvertFToS(ctx.U64, value); |
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} |
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Id EmitConvertS64F32(EmitContext& ctx, Id value) { |
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return ctx.OpConvertFToS(ctx.U64, value); |
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} |
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Id EmitConvertS64F64(EmitContext& ctx, Id value) { |
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return ctx.OpConvertFToS(ctx.U64, value); |
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} |
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Id EmitConvertU16F16(EmitContext& ctx, Id value) { |
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return ctx.OpUConvert(ctx.U32[1], ctx.OpConvertFToU(ctx.U16, value)); |
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} |
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Id EmitConvertU16F32(EmitContext& ctx, Id value) { |
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return ctx.OpUConvert(ctx.U32[1], ctx.OpConvertFToU(ctx.U16, value)); |
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} |
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Id EmitConvertU16F64(EmitContext& ctx, Id value) { |
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return ctx.OpUConvert(ctx.U32[1], ctx.OpConvertFToU(ctx.U16, value)); |
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} |
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Id EmitConvertU32F16(EmitContext& ctx, Id value) { |
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return ctx.OpConvertFToU(ctx.U32[1], value); |
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} |
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Id EmitConvertU32F32(EmitContext& ctx, Id value) { |
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return ctx.OpConvertFToU(ctx.U32[1], value); |
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} |
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Id EmitConvertU32F64(EmitContext& ctx, Id value) { |
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return ctx.OpConvertFToU(ctx.U32[1], value); |
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} |
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Id EmitConvertU64F16(EmitContext& ctx, Id value) { |
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return ctx.OpConvertFToU(ctx.U64, value); |
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} |
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Id EmitConvertU64F32(EmitContext& ctx, Id value) { |
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return ctx.OpConvertFToU(ctx.U64, value); |
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} |
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Id EmitConvertU64F64(EmitContext& ctx, Id value) { |
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return ctx.OpConvertFToU(ctx.U64, value); |
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} |
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Id EmitConvertU64U32(EmitContext& ctx, Id value) { |
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return ctx.OpUConvert(ctx.U64, value); |
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} |
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Id EmitConvertU32U64(EmitContext& ctx, Id value) { |
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return ctx.OpUConvert(ctx.U32[1], value); |
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} |
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} // namespace Shader::Backend::SPIRV
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <algorithm>
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#include "shader_recompiler/frontend/ir/ir_emitter.h"
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#include "shader_recompiler/frontend/ir/microinstruction.h"
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#include "shader_recompiler/ir_opt/passes.h"
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namespace Shader::Optimization { |
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namespace { |
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IR::Opcode Replace(IR::Opcode op) { |
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switch (op) { |
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case IR::Opcode::FPAbs16: |
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return IR::Opcode::FPAbs32; |
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case IR::Opcode::FPAdd16: |
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return IR::Opcode::FPAdd32; |
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case IR::Opcode::FPCeil16: |
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return IR::Opcode::FPCeil32; |
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case IR::Opcode::FPFloor16: |
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return IR::Opcode::FPFloor32; |
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case IR::Opcode::FPFma16: |
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return IR::Opcode::FPFma32; |
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case IR::Opcode::FPMul16: |
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return IR::Opcode::FPMul32; |
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case IR::Opcode::FPNeg16: |
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return IR::Opcode::FPNeg32; |
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case IR::Opcode::FPRoundEven16: |
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return IR::Opcode::FPRoundEven32; |
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case IR::Opcode::FPSaturate16: |
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return IR::Opcode::FPSaturate32; |
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case IR::Opcode::FPTrunc16: |
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return IR::Opcode::FPTrunc32; |
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case IR::Opcode::CompositeConstructF16x2: |
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return IR::Opcode::CompositeConstructF32x2; |
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case IR::Opcode::CompositeConstructF16x3: |
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return IR::Opcode::CompositeConstructF32x3; |
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case IR::Opcode::CompositeConstructF16x4: |
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return IR::Opcode::CompositeConstructF32x4; |
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case IR::Opcode::CompositeExtractF16x2: |
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return IR::Opcode::CompositeExtractF32x2; |
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case IR::Opcode::CompositeExtractF16x3: |
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return IR::Opcode::CompositeExtractF32x3; |
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case IR::Opcode::CompositeExtractF16x4: |
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return IR::Opcode::CompositeExtractF32x4; |
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case IR::Opcode::ConvertS16F16: |
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return IR::Opcode::ConvertS16F32; |
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case IR::Opcode::ConvertS32F16: |
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return IR::Opcode::ConvertS32F32; |
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case IR::Opcode::ConvertS64F16: |
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return IR::Opcode::ConvertS64F32; |
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case IR::Opcode::ConvertU16F16: |
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return IR::Opcode::ConvertU16F32; |
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case IR::Opcode::ConvertU32F16: |
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return IR::Opcode::ConvertU32F32; |
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case IR::Opcode::ConvertU64F16: |
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return IR::Opcode::ConvertU64F32; |
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case IR::Opcode::PackFloat2x16: |
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return IR::Opcode::PackHalf2x16; |
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case IR::Opcode::UnpackFloat2x16: |
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return IR::Opcode::UnpackHalf2x16; |
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default: |
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return op; |
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} |
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} |
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} // Anonymous namespace
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void LowerFp16ToFp32(IR::Program& program) { |
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for (IR::Function& function : program.functions) { |
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for (IR::Block* const block : function.blocks) { |
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for (IR::Inst& inst : block->Instructions()) { |
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inst.ReplaceOpcode(Replace(inst.Opcode())); |
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} |
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} |
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} |
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} |
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} // namespace Shader::Optimization
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