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@ -282,37 +282,42 @@ void Scheduler::EndRenderPass() { |
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images = renderpass_images, |
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ranges = renderpass_image_ranges](vk::CommandBuffer cmdbuf) { |
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std::array<VkImageMemoryBarrier, 9> barriers; |
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VkPipelineStageFlags src_stages = 0; |
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// Aggregate usage across all attachments in the finished render pass
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bool any_color_write = false; |
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bool any_depth_stencil_write = false; |
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VkPipelineStageFlags src_stages_union = 0; |
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for (size_t i = 0; i < num_images; ++i) { |
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const VkImageSubresourceRange& range = ranges[i]; |
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const bool is_color = (range.aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) != 0; |
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const bool is_depth_stencil = (range.aspectMask & |
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(VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) != 0; |
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const bool is_depth_stencil = |
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(range.aspectMask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) != 0; |
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VkAccessFlags src_access = 0; |
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VkPipelineStageFlags this_stage = 0; |
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VkPipelineStageFlags this_src_stage = 0; |
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if (is_color) { |
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any_color_write = true; |
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src_access |= VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT; |
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this_stage |= VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT; |
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this_src_stage |= VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT; |
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} |
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if (is_depth_stencil) { |
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any_depth_stencil_write = true; |
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src_access |= VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT; |
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this_stage |= VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | |
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VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT; |
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this_src_stage |= VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | |
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VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT; |
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} |
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src_stages |= this_stage; |
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src_stages_union |= this_src_stage; |
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barriers[i] = VkImageMemoryBarrier{ |
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.sType = VK_STRUCTURE_TYPE_IMAGE_MEMORY_BARRIER, |
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.pNext = nullptr, |
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.srcAccessMask = src_access, |
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.dstAccessMask = VK_ACCESS_SHADER_READ_BIT | VK_ACCESS_SHADER_WRITE_BIT | |
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VK_ACCESS_COLOR_ATTACHMENT_READ_BIT | VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT | |
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VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT | VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT, |
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// Assume common next use: shader reads; expand only if needed elsewhere
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.dstAccessMask = VK_ACCESS_SHADER_READ_BIT, |
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.oldLayout = VK_IMAGE_LAYOUT_GENERAL, |
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.newLayout = VK_IMAGE_LAYOUT_GENERAL, |
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.srcQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED, |
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@ -322,20 +327,29 @@ void Scheduler::EndRenderPass() { |
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}; |
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} |
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// Graft: ensure explicit fragment tests + color output stages are always synchronized (AMD/Windows fix)
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src_stages |= VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | |
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VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT | |
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VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT; |
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// AMD/Windows robustness: ensure the union includes required stages,
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// but only for aspects actually used in the pass (avoid unconditional over-sync).
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VkPipelineStageFlags src_stages = |
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(any_color_write ? VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT : 0) | |
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(any_depth_stencil_write ? (VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | |
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VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT) : 0); |
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// If you prefer to also include the accumulated union (covers mixed cases):
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src_stages |= src_stages_union; |
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cmdbuf.EndRenderPass(); |
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// Narrow destination stages to typical consumers (shader reads). Add more if needed.
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VkPipelineStageFlags dst_stages = VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT | |
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VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT; |
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cmdbuf.PipelineBarrier( |
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src_stages, |
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VK_PIPELINE_STAGE_ALL_COMMANDS_BIT, |
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dst_stages, |
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0, |
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nullptr, |
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nullptr, |
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vk::Span(barriers.data(), num_images) // Batched image barriers
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vk::Span(barriers.data(), num_images) |
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); |
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}); |
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