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@ -16,7 +16,54 @@ u32 ShaderIR::DecodeArithmeticHalf(BasicBlock& bb, u32 pc) { |
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const Instruction instr = {program_code[pc]}; |
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const auto opcode = OpCode::Decode(instr); |
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UNIMPLEMENTED(); |
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if (opcode->get().GetId() == OpCode::Id::HADD2_C || |
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opcode->get().GetId() == OpCode::Id::HADD2_R) { |
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UNIMPLEMENTED_IF(instr.alu_half.ftz != 0); |
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} |
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UNIMPLEMENTED_IF_MSG(instr.alu_half.saturate != 0, |
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"Half float saturation not implemented"); |
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const bool negate_a = |
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opcode->get().GetId() != OpCode::Id::HMUL2_R && instr.alu_half.negate_a != 0; |
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const bool negate_b = |
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opcode->get().GetId() != OpCode::Id::HMUL2_C && instr.alu_half.negate_b != 0; |
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const Node op_a = GetOperandAbsNegHalf(GetRegister(instr.gpr8), instr.alu_half.abs_a, negate_a); |
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// instr.alu_half.type_a
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Node op_b = [&]() { |
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switch (opcode->get().GetId()) { |
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case OpCode::Id::HADD2_C: |
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case OpCode::Id::HMUL2_C: |
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return GetConstBuffer(instr.cbuf34.index, instr.cbuf34.offset); |
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case OpCode::Id::HADD2_R: |
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case OpCode::Id::HMUL2_R: |
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return GetRegister(instr.gpr20); |
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default: |
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UNREACHABLE(); |
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return Immediate(0); |
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} |
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}(); |
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op_b = GetOperandAbsNegHalf(op_b, instr.alu_half.abs_b, negate_b); |
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Node value = [&]() { |
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MetaHalfArithmetic meta{true, {instr.alu_half_imm.type_a, instr.alu_half.type_b}}; |
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switch (opcode->get().GetId()) { |
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case OpCode::Id::HADD2_C: |
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case OpCode::Id::HADD2_R: |
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return Operation(OperationCode::HAdd, meta, op_a, op_b); |
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case OpCode::Id::HMUL2_C: |
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case OpCode::Id::HMUL2_R: |
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return Operation(OperationCode::HMul, meta, op_a, op_b); |
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default: |
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UNIMPLEMENTED_MSG("Unhandled half float instruction: {}", opcode->get().GetName()); |
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return Immediate(0); |
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} |
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}(); |
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value = HalfMerge(GetRegister(instr.gpr0), value, instr.alu_half.merge); |
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SetRegister(bb, instr.gpr0, value); |
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return pc; |
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} |
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