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@ -11,10 +11,20 @@ namespace Shader::Maxwell { |
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using namespace LDC; |
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namespace { |
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std::pair<IR::U32, IR::U32> Slot(IR::IREmitter& ir, Mode mode, const IR::U32& imm_index, |
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const IR::U32& reg, const IR::U32& imm) { |
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const IR::U32& reg, const IR::U32& imm_offset) { |
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switch (mode) { |
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case Mode::Default: |
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return {imm_index, ir.IAdd(reg, imm)}; |
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return {imm_index, ir.IAdd(reg, imm_offset)}; |
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case Mode::IS: { |
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// Segmented addressing mode
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// Ra+imm_offset points into a flat mapping of const buffer
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// address space
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const IR::U32 address{ir.IAdd(reg, imm_offset)}; |
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const IR::U32 index{ir.BitFieldExtract(address, ir.Imm32(16), ir.Imm32(16))}; |
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const IR::U32 offset{ir.BitFieldExtract(address, ir.Imm32(0), ir.Imm32(16))}; |
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return {ir.IAdd(index, imm_index), offset}; |
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} |
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default: |
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break; |
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} |
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