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@ -21,6 +21,7 @@ using Tegra::Shader::OpCode; |
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using Tegra::Shader::Register; |
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namespace { |
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u32 GetUniformTypeElementsCount(Tegra::Shader::UniformType uniform_type) { |
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switch (uniform_type) { |
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case Tegra::Shader::UniformType::Single: |
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@ -35,6 +36,7 @@ u32 GetUniformTypeElementsCount(Tegra::Shader::UniformType uniform_type) { |
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return 1; |
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} |
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} |
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} // Anonymous namespace
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u32 ShaderIR::DecodeMemory(NodeBlock& bb, u32 pc) { |
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@ -196,28 +198,28 @@ u32 ShaderIR::DecodeMemory(NodeBlock& bb, u32 pc) { |
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UNIMPLEMENTED_IF_MSG((instr.attribute.fmt20.immediate.Value() % sizeof(u32)) != 0, |
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"Unaligned attribute loads are not supported"); |
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u64 next_element = instr.attribute.fmt20.element; |
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auto next_index = static_cast<u64>(instr.attribute.fmt20.index.Value()); |
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u64 element = instr.attribute.fmt20.element; |
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auto index = static_cast<u64>(instr.attribute.fmt20.index.Value()); |
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const auto StoreNextElement = [&](u32 reg_offset) { |
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const auto dest = GetOutputAttribute(static_cast<Attribute::Index>(next_index), |
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next_element, GetRegister(instr.gpr39)); |
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const u32 num_words = static_cast<u32>(instr.attribute.fmt20.size.Value()) + 1; |
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for (u32 reg_offset = 0; reg_offset < num_words; ++reg_offset) { |
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Node dest; |
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if (instr.attribute.fmt20.patch) { |
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const u32 offset = static_cast<u32>(index) * 4 + static_cast<u32>(element); |
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dest = MakeNode<PatchNode>(offset); |
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} else { |
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dest = GetOutputAttribute(static_cast<Attribute::Index>(index), element, |
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GetRegister(instr.gpr39)); |
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} |
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const auto src = GetRegister(instr.gpr0.Value() + reg_offset); |
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bb.push_back(Operation(OperationCode::Assign, dest, src)); |
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// Load the next attribute element into the following register. If the element
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// to load goes beyond the vec4 size, load the first element of the next
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// attribute.
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next_element = (next_element + 1) % 4; |
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next_index = next_index + (next_element == 0 ? 1 : 0); |
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}; |
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const u32 num_words = static_cast<u32>(instr.attribute.fmt20.size.Value()) + 1; |
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for (u32 reg_offset = 0; reg_offset < num_words; ++reg_offset) { |
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StoreNextElement(reg_offset); |
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// Load the next attribute element into the following register. If the element to load
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// goes beyond the vec4 size, load the first element of the next attribute.
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element = (element + 1) % 4; |
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index = index + (element == 0 ? 1 : 0); |
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} |
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break; |
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} |
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case OpCode::Id::ST_L: |
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