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@ -1299,8 +1299,8 @@ void RasterizerVulkan::UpdateStencilFaces(Tegra::Engines::Maxwell3D::Regs& regs) |
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if (front_dirty || back_dirty) { |
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scheduler.Record([front_ref = regs.stencil_front_ref, |
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back_ref = regs.stencil_back_ref, |
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two_sided](vk::CommandBuffer cmdbuf) { |
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const bool set_back = two_sided && front_ref != back_ref; |
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is_two_sided = two_sided](vk::CommandBuffer cmdbuf) { |
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const bool set_back = is_two_sided && front_ref != back_ref; |
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cmdbuf.SetStencilReference(set_back ? VK_STENCIL_FACE_FRONT_BIT |
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: VK_STENCIL_FACE_FRONT_AND_BACK, |
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front_ref); |
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@ -1324,9 +1324,9 @@ void RasterizerVulkan::UpdateStencilFaces(Tegra::Engines::Maxwell3D::Regs& regs) |
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scheduler.Record([ |
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front_write_mask = regs.stencil_front_mask, |
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back_write_mask = regs.stencil_back_mask, |
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two_sided = regs.stencil_two_side_enable |
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is_two_sided = regs.stencil_two_side_enable |
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](vk::CommandBuffer cmdbuf) { |
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const bool set_back = two_sided && front_write_mask != back_write_mask; |
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const bool set_back = is_two_sided && front_write_mask != back_write_mask; |
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cmdbuf.SetStencilWriteMask(set_back ? VK_STENCIL_FACE_FRONT_BIT |
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: VK_STENCIL_FACE_FRONT_AND_BACK, |
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front_write_mask); |
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@ -1350,9 +1350,9 @@ void RasterizerVulkan::UpdateStencilFaces(Tegra::Engines::Maxwell3D::Regs& regs) |
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scheduler.Record([ |
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front_test_mask = regs.stencil_front_func_mask, |
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back_test_mask = regs.stencil_back_func_mask, |
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two_sided = regs.stencil_two_side_enable |
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is_two_sided = regs.stencil_two_side_enable |
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](vk::CommandBuffer cmdbuf) { |
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const bool set_back = two_sided && front_test_mask != back_test_mask; |
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const bool set_back = is_two_sided && front_test_mask != back_test_mask; |
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cmdbuf.SetStencilCompareMask(set_back ? VK_STENCIL_FACE_FRONT_BIT |
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: VK_STENCIL_FACE_FRONT_AND_BACK, |
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front_test_mask); |
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