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@ -204,7 +204,7 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, u32 pc) { |
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break; |
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} |
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case OpCode::Id::TEXS: { |
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Tegra::Shader::TextureType texture_type{instr.texs.GetTextureType()}; |
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const TextureType texture_type{instr.texs.GetTextureType()}; |
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const bool is_array{instr.texs.IsArrayTexture()}; |
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const bool depth_compare = instr.texs.UsesMiscMode(TextureMiscMode::DC); |
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const auto process_mode = instr.texs.GetTextureProcessMode(); |
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@ -373,6 +373,22 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, u32 pc) { |
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GetRegister(RZ), GetRegister(RZ))); |
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break; |
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} |
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case OpCode::Id::TLDS: { |
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const Tegra::Shader::TextureType texture_type{instr.tlds.GetTextureType()}; |
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const bool is_array{instr.tlds.IsArrayTexture()}; |
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UNIMPLEMENTED_IF_MSG(instr.tlds.UsesMiscMode(TextureMiscMode::AOFFI), |
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"AOFFI is not implemented"); |
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UNIMPLEMENTED_IF_MSG(instr.tlds.UsesMiscMode(TextureMiscMode::MZ), "MZ is not implemented"); |
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if (instr.tlds.UsesMiscMode(TextureMiscMode::NODEP)) { |
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LOG_WARNING(HW_GPU, "TMML.NODEP implementation is incomplete"); |
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} |
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const Node texture = GetTldsCode(instr, texture_type, is_array); |
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WriteTexsInstructionFloat(bb, instr, texture); |
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break; |
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} |
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default: |
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UNIMPLEMENTED_MSG("Unhandled memory instruction: {}", opcode->get().GetName()); |
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} |
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@ -576,22 +592,59 @@ Node ShaderIR::GetTld4Code(Instruction instr, TextureType texture_type, bool dep |
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for (size_t i = 0; i < coord_count; ++i) { |
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params.push_back(GetRegister(coord_register + i)); |
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} |
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std::size_t array_offset{}; |
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std::optional<u32> array_offset; |
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if (is_array) { |
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array_offset = params.size(); |
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array_offset = static_cast<u32>(params.size()); |
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params.push_back(GetRegister(array_register)); |
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} |
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const auto& sampler = GetSampler(instr.sampler, texture_type, is_array, depth_compare); |
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std::optional<u32> array_offset_value; |
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if (is_array) |
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array_offset_value = static_cast<u32>(array_offset); |
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MetaTexture meta{sampler, static_cast<u32>(params.size()), array_offset_value}; |
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MetaTexture meta{sampler, static_cast<u32>(params.size()), array_offset}; |
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return Operation(OperationCode::F4TextureGather, std::move(meta), std::move(params)); |
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} |
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Node ShaderIR::GetTldsCode(Instruction instr, TextureType texture_type, bool is_array) { |
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const std::size_t type_coord_count = GetCoordCount(texture_type); |
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const std::size_t total_coord_count = type_coord_count + (is_array ? 1 : 0); |
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const bool lod_enabled = instr.tlds.GetTextureProcessMode() == TextureProcessMode::LL; |
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// If enabled arrays index is always stored in the gpr8 field
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const u64 array_register = instr.gpr8.Value(); |
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// if is array gpr20 is used
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const u64 coord_register = is_array ? instr.gpr20.Value() : instr.gpr8.Value(); |
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const u64 last_coord_register = |
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((type_coord_count > 2) || (type_coord_count == 2 && !lod_enabled)) && !is_array |
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? static_cast<u64>(instr.gpr20.Value()) |
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: coord_register + 1; |
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std::vector<Node> params; |
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for (std::size_t i = 0; i < type_coord_count; ++i) { |
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const bool last = (i == (type_coord_count - 1)) && (type_coord_count > 1); |
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params.push_back(GetRegister(last ? last_coord_register : coord_register + i)); |
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} |
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std::optional<u32> array_offset; |
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if (is_array) { |
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array_offset = static_cast<u32>(params.size()); |
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params.push_back(GetRegister(array_register)); |
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} |
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const auto coords_count = static_cast<u32>(params.size()); |
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if (lod_enabled) { |
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// When lod is used always is in grp20
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params.push_back(GetRegister(instr.gpr20)); |
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} else { |
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params.push_back(Immediate(0)); |
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} |
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const auto& sampler = GetSampler(instr.sampler, texture_type, is_array, false); |
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MetaTexture meta{sampler, coords_count, array_offset}; |
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return Operation(OperationCode::F4TexelFetch, std::move(meta), std::move(params)); |
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} |
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std::tuple<std::size_t, std::size_t> ShaderIR::ValidateAndGetCoordinateElement( |
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TextureType texture_type, bool depth_compare, bool is_array, bool lod_bias_enabled, |
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std::size_t max_coords, std::size_t max_inputs) { |
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