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ARM: Integrate SkyEye faster "dyncom" interpreter.
ARM: Integrate SkyEye faster "dyncom" interpreter.
Fixed typo (make protected member public) Added license header back in. I originally removed this because I mostly rewrote the file, but meh ARM: Fixed a type error in dyncom interpreter. ARM: Updated dyncom to use unique_ptr for internal ARM state.pull/15/merge
bunnei
11 years ago
20 changed files with 8230 additions and 75 deletions
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19src/core/CMakeLists.txt
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164src/core/arm/dyncom/arm_dyncom.cpp
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90src/core/arm/dyncom/arm_dyncom.h
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402src/core/arm/dyncom/arm_dyncom_dec.cpp
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155src/core/arm/dyncom/arm_dyncom_dec.h
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6559src/core/arm/dyncom/arm_dyncom_interpreter.cpp
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7src/core/arm/dyncom/arm_dyncom_interpreter.h
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120src/core/arm/dyncom/arm_dyncom_run.cpp
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55src/core/arm/dyncom/arm_dyncom_run.h
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521src/core/arm/dyncom/arm_dyncom_thumb.cpp
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51src/core/arm/dyncom/arm_dyncom_thumb.h
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2src/core/arm/interpreter/arm_interpreter.h
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15src/core/arm/interpreter/armsupp.cpp
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4src/core/arm/skyeye_common/arm_regformat.h
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5src/core/arm/skyeye_common/armcpu.h
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9src/core/arm/skyeye_common/armos.h
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4src/core/arm/skyeye_common/skyeye_defs.h
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55src/core/arm/skyeye_common/skyeye_types.h
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48src/core/arm/skyeye_common/vfp/vfpinstr.cpp
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20src/core/hle/coprocessor.h
@ -0,0 +1,164 @@ |
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// Copyright 2014 Citra Emulator Project
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// Licensed under GPLv2
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// Refer to the license.txt file included.
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#include "core/arm/skyeye_common/armcpu.h"
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#include "core/arm/skyeye_common/armemu.h"
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#include "core/arm/skyeye_common/vfp/vfp.h"
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#include "core/arm/dyncom/arm_dyncom.h"
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#include "core/arm/dyncom/arm_dyncom_interpreter.h"
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const static cpu_config_t s_arm11_cpu_info = { |
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"armv6", "arm11", 0x0007b000, 0x0007f000, NONCACHE |
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}; |
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ARM_DynCom::ARM_DynCom() : ticks(0) { |
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state = std::unique_ptr<ARMul_State>(new ARMul_State); |
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ARMul_EmulateInit(); |
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memset(state.get(), 0, sizeof(ARMul_State)); |
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ARMul_NewState((ARMul_State*)state.get()); |
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state->abort_model = 0; |
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state->cpu = (cpu_config_t*)&s_arm11_cpu_info; |
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state->bigendSig = LOW; |
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ARMul_SelectProcessor(state.get(), ARM_v6_Prop | ARM_v5_Prop | ARM_v5e_Prop); |
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state->lateabtSig = LOW; |
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mmu_init(state); |
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// Reset the core to initial state
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ARMul_CoProInit(state.get()); |
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ARMul_Reset(state.get()); |
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state->NextInstr = RESUME; // NOTE: This will be overwritten by LoadContext
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state->Emulate = 3; |
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state->pc = state->Reg[15] = 0x00000000; |
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state->Reg[13] = 0x10000000; // Set stack pointer to the top of the stack
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state->servaddr = 0xFFFF0000; |
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state->NirqSig = HIGH; |
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VFPInit(state.get()); // Initialize the VFP
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ARMul_EmulateInit(); |
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} |
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ARM_DynCom::~ARM_DynCom() { |
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} |
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/**
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* Set the Program Counter to an address |
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* @param addr Address to set PC to |
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*/ |
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void ARM_DynCom::SetPC(u32 pc) { |
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state->pc = state->Reg[15] = pc; |
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} |
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/*
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* Get the current Program Counter |
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* @return Returns current PC |
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*/ |
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u32 ARM_DynCom::GetPC() const { |
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return state->pc; |
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} |
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/**
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* Get an ARM register |
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* @param index Register index (0-15) |
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* @return Returns the value in the register |
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*/ |
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u32 ARM_DynCom::GetReg(int index) const { |
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return state->Reg[index]; |
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} |
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/**
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* Set an ARM register |
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* @param index Register index (0-15) |
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* @param value Value to set register to |
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*/ |
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void ARM_DynCom::SetReg(int index, u32 value) { |
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state->Reg[index] = value; |
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} |
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/**
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* Get the current CPSR register |
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* @return Returns the value of the CPSR register |
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*/ |
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u32 ARM_DynCom::GetCPSR() const { |
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return state->Cpsr; |
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} |
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/**
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* Set the current CPSR register |
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* @param cpsr Value to set CPSR to |
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*/ |
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void ARM_DynCom::SetCPSR(u32 cpsr) { |
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state->Cpsr = cpsr; |
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} |
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/**
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* Returns the number of clock ticks since the last reset |
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* @return Returns number of clock ticks |
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*/ |
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u64 ARM_DynCom::GetTicks() const { |
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return ticks; |
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} |
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/**
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* Executes the given number of instructions |
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* @param num_instructions Number of instructions to executes |
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*/ |
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void ARM_DynCom::ExecuteInstructions(int num_instructions) { |
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ticks += num_instructions; |
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state->NumInstrsToExecute = num_instructions; |
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InterpreterMainLoop(state.get()); |
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} |
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/**
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* Saves the current CPU context |
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* @param ctx Thread context to save |
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* @todo Do we need to save Reg[15] and NextInstr? |
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*/ |
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void ARM_DynCom::SaveContext(ThreadContext& ctx) { |
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memcpy(ctx.cpu_registers, state->Reg, sizeof(ctx.cpu_registers)); |
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memcpy(ctx.fpu_registers, state->ExtReg, sizeof(ctx.fpu_registers)); |
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ctx.sp = state->Reg[13]; |
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ctx.lr = state->Reg[14]; |
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ctx.pc = state->pc; |
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ctx.cpsr = state->Cpsr; |
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ctx.fpscr = state->VFP[1]; |
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ctx.fpexc = state->VFP[2]; |
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ctx.reg_15 = state->Reg[15]; |
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ctx.mode = state->NextInstr; |
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} |
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/**
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* Loads a CPU context |
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* @param ctx Thread context to load |
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* @param Do we need to load Reg[15] and NextInstr? |
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*/ |
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void ARM_DynCom::LoadContext(const ThreadContext& ctx) { |
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memcpy(state->Reg, ctx.cpu_registers, sizeof(ctx.cpu_registers)); |
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memcpy(state->ExtReg, ctx.fpu_registers, sizeof(ctx.fpu_registers)); |
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state->Reg[13] = ctx.sp; |
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state->Reg[14] = ctx.lr; |
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state->pc = ctx.pc; |
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state->Cpsr = ctx.cpsr; |
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state->VFP[1] = ctx.fpscr; |
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state->VFP[2] = ctx.fpexc; |
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state->Reg[15] = ctx.reg_15; |
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state->NextInstr = ctx.mode; |
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} |
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/// Prepare core for thread reschedule (if needed to correctly handle state)
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void ARM_DynCom::PrepareReschedule() { |
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state->NumInstrsToExecute = 0; |
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} |
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@ -0,0 +1,90 @@ |
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// Copyright 2014 Citra Emulator Project |
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// Licensed under GPLv2 |
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// Refer to the license.txt file included. |
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#pragma once |
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#include <memory> |
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#include "common/common_types.h" |
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#include "core/arm/arm_interface.h" |
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#include "core/arm/skyeye_common/armdefs.h" |
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class ARM_DynCom final : virtual public ARM_Interface { |
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public: |
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ARM_DynCom(); |
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~ARM_DynCom(); |
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/** |
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* Set the Program Counter to an address |
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* @param addr Address to set PC to |
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*/ |
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void SetPC(u32 pc); |
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/* |
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* Get the current Program Counter |
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* @return Returns current PC |
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*/ |
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u32 GetPC() const; |
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/** |
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* Get an ARM register |
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* @param index Register index (0-15) |
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* @return Returns the value in the register |
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*/ |
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u32 GetReg(int index) const; |
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/** |
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* Set an ARM register |
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* @param index Register index (0-15) |
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* @param value Value to set register to |
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*/ |
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void SetReg(int index, u32 value); |
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/** |
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* Get the current CPSR register |
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* @return Returns the value of the CPSR register |
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*/ |
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u32 GetCPSR() const; |
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/** |
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* Set the current CPSR register |
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* @param cpsr Value to set CPSR to |
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*/ |
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void SetCPSR(u32 cpsr); |
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/** |
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* Returns the number of clock ticks since the last reset |
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* @return Returns number of clock ticks |
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*/ |
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u64 GetTicks() const; |
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/** |
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* Saves the current CPU context |
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* @param ctx Thread context to save |
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*/ |
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void SaveContext(ThreadContext& ctx); |
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/** |
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* Loads a CPU context |
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* @param ctx Thread context to load |
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*/ |
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void LoadContext(const ThreadContext& ctx); |
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/// Prepare core for thread reschedule (if needed to correctly handle state) |
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void PrepareReschedule(); |
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/** |
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* Executes the given number of instructions |
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* @param num_instructions Number of instructions to executes |
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*/ |
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void ExecuteInstructions(int num_instructions); |
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private: |
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std::unique_ptr<ARMul_State> state; |
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u64 ticks; |
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}; |
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@ -0,0 +1,402 @@ |
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/* Copyright (C)
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* 2012 - Michael.Kang blackfin.kang@gmail.com |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License |
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* as published by the Free Software Foundation; either version 2 |
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* of the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
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* |
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*/ |
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/**
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* @file arm_dyncom_dec.cpp |
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* @brief Some common utility for arm decoder |
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* @author Michael.Kang blackfin.kang@gmail.com |
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* @version 7849 |
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* @date 2012-03-15 |
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*/ |
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#include "core/arm/skyeye_common/arm_regformat.h"
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#include "core/arm/skyeye_common/armdefs.h"
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#include "core/arm/dyncom/arm_dyncom_dec.h"
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const ISEITEM arm_instruction[] = { |
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#define VFP_DECODE
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#include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
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#undef VFP_DECODE
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{"srs" , 4 , 6 , 25, 31, 0x0000007c, 22, 22, 0x00000001, 16, 20, 0x0000000d, 8, 11, 0x00000005}, |
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{"rfe" , 4 , 6 , 25, 31, 0x0000007c, 22, 22, 0x00000000, 20, 20, 0x00000001, 8, 11, 0x0000000a}, |
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{"bkpt" , 2 , 3 , 20, 31, 0x00000e12, 4, 7, 0x00000007}, |
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{"blx" , 1 , 3 , 25, 31, 0x0000007d}, |
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{"cps" , 3 , 6 , 20, 31, 0x00000f10, 16, 16, 0x00000000, 5, 5, 0x00000000}, |
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{"pld" , 4 , 4 , 26, 31, 0x0000003d, 24, 24, 0x00000001, 20, 22, 0x00000005, 12, 15, 0x0000000f}, |
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{"setend" , 2 , 6 , 16, 31, 0x0000f101, 4, 7, 0x00000000}, |
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{"clrex" , 1 , 6 , 0, 31, 0xf57ff01f}, |
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{"rev16" , 2 , 6 , 16, 27, 0x000006bf, 4, 11, 0x000000fb}, |
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{"usad8" , 3 , 6 , 20, 27, 0x00000078, 12, 15, 0x0000000f, 4, 7, 0x00000001}, |
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{"sxtb" , 2 , 6 , 16, 27, 0x000006af, 4, 7, 0x00000007}, |
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{"uxtb" , 2 , 6 , 16, 27, 0x000006ef, 4, 7, 0x00000007}, |
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{"sxth" , 2 , 6 , 16, 27, 0x000006bf, 4, 7, 0x00000007}, |
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{"sxtb16" , 2 , 6 , 16, 27, 0x0000068f, 4, 7, 0x00000007}, |
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{"uxth" , 2 , 6 , 16, 27, 0x000006ff, 4, 7, 0x00000007}, |
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{"uxtb16" , 2 , 6 , 16, 27, 0x000006cf, 4, 7, 0x00000007}, |
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{"cpy" , 2 , 6 , 20, 27, 0x0000001a, 4, 11, 0x00000000}, |
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{"uxtab" , 2 , 6 , 20, 27, 0x0000006e, 4, 9, 0x00000007}, |
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{"ssub8" , 2 , 6 , 20, 27, 0x00000061, 4, 7, 0x0000000f}, |
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{"shsub8" , 2 , 6 , 20, 27, 0x00000063, 4, 7, 0x0000000f}, |
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{"ssubaddx" , 2 , 6 , 20, 27, 0x00000061, 4, 7, 0x00000005}, |
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{"strex" , 2 , 6 , 20, 27, 0x00000018, 4, 7, 0x00000009}, |
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{"strexb" , 2 , 7 , 20, 27, 0x0000001c, 4, 7, 0x00000009}, |
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{"swp" , 2 , 0 , 20, 27, 0x00000010, 4, 7, 0x00000009}, |
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{"swpb" , 2 , 0 , 20, 27, 0x00000014, 4, 7, 0x00000009}, |
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{"ssub16" , 2 , 6 , 20, 27, 0x00000061, 4, 7, 0x00000007}, |
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{"ssat16" , 2 , 6 , 20, 27, 0x0000006a, 4, 7, 0x00000003}, |
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{"shsubaddx" , 2 , 6 , 20, 27, 0x00000063, 4, 7, 0x00000005}, |
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{"qsubaddx" , 2 , 6 , 20, 27, 0x00000062, 4, 7, 0x00000005}, |
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{"shaddsubx" , 2 , 6 , 20, 27, 0x00000063, 4, 7, 0x00000003}, |
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{"shadd8" , 2 , 6 , 20, 27, 0x00000063, 4, 7, 0x00000009}, |
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{"shadd16" , 2 , 6 , 20, 27, 0x00000063, 4, 7, 0x00000001}, |
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{"sel" , 2 , 6 , 20, 27, 0x00000068, 4, 7, 0x0000000b}, |
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{"saddsubx" , 2 , 6 , 20, 27, 0x00000061, 4, 7, 0x00000003}, |
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{"sadd8" , 2 , 6 , 20, 27, 0x00000061, 4, 7, 0x00000009}, |
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{"sadd16" , 2 , 6 , 20, 27, 0x00000061, 4, 7, 0x00000001}, |
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{"shsub16" , 2 , 6 , 20, 27, 0x00000063, 4, 7, 0x00000007}, |
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{"umaal" , 2 , 6 , 20, 27, 0x00000004, 4, 7, 0x00000009}, |
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{"uxtab16" , 2 , 6 , 20, 27, 0x0000006c, 4, 7, 0x00000007}, |
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{"usubaddx" , 2 , 6 , 20, 27, 0x00000065, 4, 7, 0x00000005}, |
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{"usub8" , 2 , 6 , 20, 27, 0x00000065, 4, 7, 0x0000000f}, |
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{"usub16" , 2 , 6 , 20, 27, 0x00000065, 4, 7, 0x00000007}, |
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{"usat16" , 2 , 6 , 20, 27, 0x0000006e, 4, 7, 0x00000003}, |
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{"usada8" , 2 , 6 , 20, 27, 0x00000078, 4, 7, 0x00000001}, |
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{"uqsubaddx" , 2 , 6 , 20, 27, 0x00000066, 4, 7, 0x00000005}, |
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{"uqsub8" , 2 , 6 , 20, 27, 0x00000066, 4, 7, 0x0000000f}, |
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{"uqsub16" , 2 , 6 , 20, 27, 0x00000066, 4, 7, 0x00000007}, |
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{"uqaddsubx" , 2 , 6 , 20, 27, 0x00000066, 4, 7, 0x00000003}, |
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{"uqadd8" , 2 , 6 , 20, 27, 0x00000066, 4, 7, 0x00000009}, |
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{"uqadd16" , 2 , 6 , 20, 27, 0x00000066, 4, 7, 0x00000001}, |
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{"sxtab" , 2 , 6 , 20, 27, 0x0000006a, 4, 7, 0x00000007}, |
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{"uhsubaddx" , 2 , 6 , 20, 27, 0x00000067, 4, 7, 0x00000005}, |
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{"uhsub8" , 2 , 6 , 20, 27, 0x00000067, 4, 7, 0x0000000f}, |
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{"uhsub16" , 2 , 6 , 20, 27, 0x00000067, 4, 7, 0x00000007}, |
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{"uhaddsubx" , 2 , 6 , 20, 27, 0x00000067, 4, 7, 0x00000003}, |
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{"uhadd8" , 2 , 6 , 20, 27, 0x00000067, 4, 7, 0x00000009}, |
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{"uhadd16" , 2 , 6 , 20, 27, 0x00000067, 4, 7, 0x00000001}, |
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{"uaddsubx" , 2 , 6 , 20, 27, 0x00000065, 4, 7, 0x00000003}, |
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{"uadd8" , 2 , 6 , 20, 27, 0x00000065, 4, 7, 0x00000009}, |
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{"uadd16" , 2 , 6 , 20, 27, 0x00000065, 4, 7, 0x00000001}, |
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{"sxtah" , 2 , 6 , 20, 27, 0x0000006b, 4, 7, 0x00000007}, |
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{"sxtab16" , 2 , 6 , 20, 27, 0x00000068, 4, 7, 0x00000007}, |
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{"qadd8" , 2 , 6 , 20, 27, 0x00000062, 4, 7, 0x00000009}, |
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{"bxj" , 2 , 5 , 20, 27, 0x00000012, 4, 7, 0x00000002}, |
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{"clz" , 2 , 3 , 20, 27, 0x00000016, 4, 7, 0x00000001}, |
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{"uxtah" , 2 , 6 , 20, 27, 0x0000006f, 4, 7, 0x00000007}, |
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{"bx" , 2 , 2 , 20, 27, 0x00000012, 4, 7, 0x00000001}, |
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{"rev" , 2 , 6 , 20, 27, 0x0000006b, 4, 7, 0x00000003}, |
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{"blx" , 2 , 3 , 20, 27, 0x00000012, 4, 7, 0x00000003}, |
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{"revsh" , 2 , 6 , 20, 27, 0x0000006f, 4, 7, 0x0000000b}, |
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{"qadd" , 2 , 4 , 20, 27, 0x00000010, 4, 7, 0x00000005}, |
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{"qadd16" , 2 , 6 , 20, 27, 0x00000062, 4, 7, 0x00000001}, |
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{"qaddsubx" , 2 , 6 , 20, 27, 0x00000062, 4, 7, 0x00000003}, |
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{"ldrex" , 2 , 0 , 20, 27, 0x00000019, 4, 7, 0x00000009}, |
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{"qdadd" , 2 , 4 , 20, 27, 0x00000014, 4, 7, 0x00000005}, |
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{"qdsub" , 2 , 4 , 20, 27, 0x00000016, 4, 7, 0x00000005}, |
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{"qsub" , 2 , 4 , 20, 27, 0x00000012, 4, 7, 0x00000005}, |
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{"ldrexb" , 2 , 7 , 20, 27, 0x0000001d, 4, 7, 0x00000009}, |
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{"qsub8" , 2 , 6 , 20, 27, 0x00000062, 4, 7, 0x0000000f}, |
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{"qsub16" , 2 , 6 , 20, 27, 0x00000062, 4, 7, 0x00000007}, |
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{"smuad" , 4 , 6 , 20, 27, 0x00000070, 12, 15, 0x0000000f, 6, 7, 0x00000000, 4, 4, 0x00000001}, |
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{"smmul" , 4 , 6 , 20, 27, 0x00000075, 12, 15, 0x0000000f, 6, 7, 0x00000000, 4, 4, 0x00000001}, |
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{"smusd" , 4 , 6 , 20, 27, 0x00000070, 12, 15, 0x0000000f, 6, 7, 0x00000001, 4, 4, 0x00000001}, |
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{"smlsd" , 3 , 6 , 20, 27, 0x00000070, 6, 7, 0x00000001, 4, 4, 0x00000001}, |
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{"smlsld" , 3 , 6 , 20, 27, 0x00000074, 6, 7, 0x00000001, 4, 4, 0x00000001}, |
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{"smmla" , 3 , 6 , 20, 27, 0x00000075, 6, 7, 0x00000000, 4, 4, 0x00000001}, |
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{"smmls" , 3 , 6 , 20, 27, 0x00000075, 6, 7, 0x00000003, 4, 4, 0x00000001}, |
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{"smlald" , 3 , 6 , 20, 27, 0x00000074, 6, 7, 0x00000000, 4, 4, 0x00000001}, |
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{"smlad" , 3 , 6 , 20, 27, 0x00000070, 6, 7, 0x00000000, 4, 4, 0x00000001}, |
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{"smlaw" , 3 , 4 , 20, 27, 0x00000012, 7, 7, 0x00000001, 4, 5, 0x00000000}, |
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{"smulw" , 3 , 4 , 20, 27, 0x00000012, 7, 7, 0x00000001, 4, 5, 0x00000002}, |
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{"pkhtb" , 2 , 6 , 20, 27, 0x00000068, 4, 6, 0x00000005}, |
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{"pkhbt" , 2 , 6 , 20, 27, 0x00000068, 4, 6, 0x00000001}, |
|||
{"smul" , 3 , 4 , 20, 27, 0x00000016, 7, 7, 0x00000001, 4, 4, 0x00000000}, |
|||
{"smlalxy" , 3 , 4 , 20, 27, 0x00000014, 7, 7, 0x00000001, 4, 4, 0x00000000}, |
|||
// {"smlal" , 2 , 4 , 21, 27, 0x00000007, 4, 7, 0x00000009},
|
|||
{"smla" , 3 , 4 , 20, 27, 0x00000010, 7, 7, 0x00000001, 4, 4, 0x00000000}, |
|||
{"mcrr" , 1 , 6 , 20, 27, 0x000000c4}, |
|||
{"mrrc" , 1 , 6 , 20, 27, 0x000000c5}, |
|||
{"cmp" , 2 , 0 , 26, 27, 0x00000000, 20, 24, 0x00000015}, |
|||
{"tst" , 2 , 0 , 26, 27, 0x00000000, 20, 24, 0x00000011}, |
|||
{"teq" , 2 , 0 , 26, 27, 0x00000000, 20, 24, 0x00000013}, |
|||
{"cmn" , 2 , 0 , 26, 27, 0x00000000, 20, 24, 0x00000017}, |
|||
{"smull" , 2 , 0 , 21, 27, 0x00000006, 4, 7, 0x00000009}, |
|||
{"umull" , 2 , 0 , 21, 27, 0x00000004, 4, 7, 0x00000009}, |
|||
{"umlal" , 2 , 0 , 21, 27, 0x00000005, 4, 7, 0x00000009}, |
|||
{"smlal" , 2 , 0 , 21, 27, 0x00000007, 4, 7, 0x00000009}, |
|||
{"mul" , 2 , 0 , 21, 27, 0x00000000, 4, 7, 0x00000009}, |
|||
{"mla" , 2 , 0 , 21, 27, 0x00000001, 4, 7, 0x00000009}, |
|||
{"ssat" , 2 , 6 , 21, 27, 0x00000035, 4, 5, 0x00000001}, |
|||
{"usat" , 2 , 6 , 21, 27, 0x00000037, 4, 5, 0x00000001}, |
|||
{"mrs" , 4 , 0 , 23, 27, 0x00000002, 20, 21, 0x00000000, 16, 19, 0x0000000f, 0, 11, 0x00000000}, |
|||
{"msr" , 3 , 0 , 23, 27, 0x00000002, 20, 21, 0x00000002, 4, 7, 0x00000000}, |
|||
{"and" , 2 , 0 , 26, 27, 0x00000000, 21, 24, 0x00000000}, |
|||
{"bic" , 2 , 0 , 26, 27, 0x00000000, 21, 24, 0x0000000e}, |
|||
{"ldm" , 3 , 0 , 25, 27, 0x00000004, 20, 22, 0x00000005, 15, 15, 0x00000000}, |
|||
{"eor" , 2 , 0 , 26, 27, 0x00000000, 21, 24, 0x00000001}, |
|||
{"add" , 2 , 0 , 26, 27, 0x00000000, 21, 24, 0x00000004}, |
|||
{"rsb" , 2 , 0 , 26, 27, 0x00000000, 21, 24, 0x00000003}, |
|||
{"rsc" , 2 , 0 , 26, 27, 0x00000000, 21, 24, 0x00000007}, |
|||
{"sbc" , 2 , 0 , 26, 27, 0x00000000, 21, 24, 0x00000006}, |
|||
{"adc" , 2 , 0 , 26, 27, 0x00000000, 21, 24, 0x00000005}, |
|||
{"sub" , 2 , 0 , 26, 27, 0x00000000, 21, 24, 0x00000002}, |
|||
{"orr" , 2 , 0 , 26, 27, 0x00000000, 21, 24, 0x0000000c}, |
|||
{"mvn" , 2 , 0 , 26, 27, 0x00000000, 21, 24, 0x0000000f}, |
|||
{"mov" , 2 , 0 , 26, 27, 0x00000000, 21, 24, 0x0000000d}, |
|||
{"stm" , 2 , 0 , 25, 27, 0x00000004, 20, 22, 0x00000004}, |
|||
{"ldm" , 4 , 0 , 25, 27, 0x00000004, 22, 22, 0x00000001, 20, 20, 0x00000001, 15, 15, 0x00000001}, |
|||
{"ldrsh" , 3 , 2 , 25, 27, 0x00000000, 20, 20, 0x00000001, 4, 7, 0x0000000f}, |
|||
{"stm" , 3 , 0 , 25, 27, 0x00000004, 22, 22, 0x00000000, 20, 20, 0x00000000}, |
|||
{"ldm" , 3 , 0 , 25, 27, 0x00000004, 22, 22, 0x00000000, 20, 20, 0x00000001}, |
|||
{"ldrsb" , 3 , 2 , 25, 27, 0x00000000, 20, 20, 0x00000001, 4, 7, 0x0000000d}, |
|||
{"strd" , 3 , 4 , 25, 27, 0x00000000, 20, 20, 0x00000000, 4, 7, 0x0000000f}, |
|||
{"ldrh" , 3 , 0 , 25, 27, 0x00000000, 20, 20, 0x00000001, 4, 7, 0x0000000b}, |
|||
{"strh" , 3 , 0 , 25, 27, 0x00000000, 20, 20, 0x00000000, 4, 7, 0x0000000b}, |
|||
{"ldrd" , 3 , 4 , 25, 27, 0x00000000, 20, 20, 0x00000000, 4, 7, 0x0000000d}, |
|||
{"strt" , 3 , 0 , 26, 27, 0x00000001, 24, 24, 0x00000000, 20, 22, 0x00000002}, |
|||
{"strbt" , 3 , 0 , 26, 27, 0x00000001, 24, 24, 0x00000000, 20, 22, 0x00000006}, |
|||
{"ldrbt" , 3 , 0 , 26, 27, 0x00000001, 24, 24, 0x00000000, 20, 22, 0x00000007}, |
|||
{"ldrt" , 3 , 0 , 26, 27, 0x00000001, 24, 24, 0x00000000, 20, 22, 0x00000003}, |
|||
{"mrc" , 3 , 6 , 24, 27, 0x0000000e, 20, 20, 0x00000001, 4, 4, 0x00000001}, |
|||
{"mcr" , 3 , 0 , 24, 27, 0x0000000e, 20, 20, 0x00000000, 4, 4, 0x00000001}, |
|||
{"msr" , 2 , 0 , 23, 27, 0x00000006, 20, 21, 0x00000002}, |
|||
{"ldrb" , 3 , 0 , 26, 27, 0x00000001, 22, 22, 0x00000001, 20, 20, 0x00000001}, |
|||
{"strb" , 3 , 0 , 26, 27, 0x00000001, 22, 22, 0x00000001, 20, 20, 0x00000000}, |
|||
{"ldr" , 4 , 0 , 28, 31, 0x0000000e, 26, 27, 0x00000001, 22, 22, 0x00000000, 20, 20, 0x00000001}, |
|||
{"ldrcond" , 3 , 0 , 26, 27, 0x00000001, 22, 22, 0x00000000, 20, 20, 0x00000001}, |
|||
{"str" , 3 , 0 , 26, 27, 0x00000001, 22, 22, 0x00000000, 20, 20, 0x00000000}, |
|||
{"cdp" , 2 , 0 , 24, 27, 0x0000000e, 4, 4, 0x00000000}, |
|||
{"stc" , 2 , 0 , 25, 27, 0x00000006, 20, 20, 0x00000000}, |
|||
{"ldc" , 2 , 0 , 25, 27, 0x00000006, 20, 20, 0x00000001}, |
|||
{"swi" , 1 , 0 , 24, 27, 0x0000000f}, |
|||
{"bbl" , 1 , 0 , 25, 27, 0x00000005}, |
|||
}; |
|||
|
|||
const ISEITEM arm_exclusion_code[] = { |
|||
#define VFP_DECODE_EXCLUSION
|
|||
#include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
|
|||
#undef VFP_DECODE_EXCLUSION
|
|||
{"srs" , 0 , 6 , 0}, |
|||
{"rfe" , 0 , 6 , 0}, |
|||
{"bkpt" , 0 , 3 , 0}, |
|||
{"blx" , 0 , 3 , 0}, |
|||
{"cps" , 0 , 6 , 0}, |
|||
{"pld" , 0 , 4 , 0}, |
|||
{"setend" , 0 , 6 , 0}, |
|||
{"clrex" , 0 , 6 , 0}, |
|||
{"rev16" , 0 , 6 , 0}, |
|||
{"usad8" , 0 , 6 , 0}, |
|||
{"sxtb" , 0 , 6 , 0}, |
|||
{"uxtb" , 0 , 6 , 0}, |
|||
{"sxth" , 0 , 6 , 0}, |
|||
{"sxtb16" , 0 , 6 , 0}, |
|||
{"uxth" , 0 , 6 , 0}, |
|||
{"uxtb16" , 0 , 6 , 0}, |
|||
{"cpy" , 0 , 6 , 0}, |
|||
{"uxtab" , 0 , 6 , 0}, |
|||
{"ssub8" , 0 , 6 , 0}, |
|||
{"shsub8" , 0 , 6 , 0}, |
|||
{"ssubaddx" , 0 , 6 , 0}, |
|||
{"strex" , 0 , 6 , 0}, |
|||
{"strexb" , 0 , 7 , 0}, |
|||
{"swp" , 0 , 0 , 0}, |
|||
{"swpb" , 0 , 0 , 0}, |
|||
{"ssub16" , 0 , 6 , 0}, |
|||
{"ssat16" , 0 , 6 , 0}, |
|||
{"shsubaddx" , 0 , 6 , 0}, |
|||
{"qsubaddx" , 0 , 6 , 0}, |
|||
{"shaddsubx" , 0 , 6 , 0}, |
|||
{"shadd8" , 0 , 6 , 0}, |
|||
{"shadd16" , 0 , 6 , 0}, |
|||
{"sel" , 0 , 6 , 0}, |
|||
{"saddsubx" , 0 , 6 , 0}, |
|||
{"sadd8" , 0 , 6 , 0}, |
|||
{"sadd16" , 0 , 6 , 0}, |
|||
{"shsub16" , 0 , 6 , 0}, |
|||
{"umaal" , 0 , 6 , 0}, |
|||
{"uxtab16" , 0 , 6 , 0}, |
|||
{"usubaddx" , 0 , 6 , 0}, |
|||
{"usub8" , 0 , 6 , 0}, |
|||
{"usub16" , 0 , 6 , 0}, |
|||
{"usat16" , 0 , 6 , 0}, |
|||
{"usada8" , 0 , 6 , 0}, |
|||
{"uqsubaddx" , 0 , 6 , 0}, |
|||
{"uqsub8" , 0 , 6 , 0}, |
|||
{"uqsub16" , 0 , 6 , 0}, |
|||
{"uqaddsubx" , 0 , 6 , 0}, |
|||
{"uqadd8" , 0 , 6 , 0}, |
|||
{"uqadd16" , 0 , 6 , 0}, |
|||
{"sxtab" , 0 , 6 , 0}, |
|||
{"uhsubaddx" , 0 , 6 , 0}, |
|||
{"uhsub8" , 0 , 6 , 0}, |
|||
{"uhsub16" , 0 , 6 , 0}, |
|||
{"uhaddsubx" , 0 , 6 , 0}, |
|||
{"uhadd8" , 0 , 6 , 0}, |
|||
{"uhadd16" , 0 , 6 , 0}, |
|||
{"uaddsubx" , 0 , 6 , 0}, |
|||
{"uadd8" , 0 , 6 , 0}, |
|||
{"uadd16" , 0 , 6 , 0}, |
|||
{"sxtah" , 0 , 6 , 0}, |
|||
{"sxtab16" , 0 , 6 , 0}, |
|||
{"qadd8" , 0 , 6 , 0}, |
|||
{"bxj" , 0 , 5 , 0}, |
|||
{"clz" , 0 , 3 , 0}, |
|||
{"uxtah" , 0 , 6 , 0}, |
|||
{"bx" , 0 , 2 , 0}, |
|||
{"rev" , 0 , 6 , 0}, |
|||
{"blx" , 0 , 3 , 0}, |
|||
{"revsh" , 0 , 6 , 0}, |
|||
{"qadd" , 0 , 4 , 0}, |
|||
{"qadd16" , 0 , 6 , 0}, |
|||
{"qaddsubx" , 0 , 6 , 0}, |
|||
{"ldrex" , 0 , 0 , 0}, |
|||
{"qdadd" , 0 , 4 , 0}, |
|||
{"qdsub" , 0 , 4 , 0}, |
|||
{"qsub" , 0 , 4 , 0}, |
|||
{"ldrexb" , 0 , 7 , 0}, |
|||
{"qsub8" , 0 , 6 , 0}, |
|||
{"qsub16" , 0 , 6 , 0}, |
|||
{"smuad" , 0 , 6 , 0}, |
|||
{"smmul" , 0 , 6 , 0}, |
|||
{"smusd" , 0 , 6 , 0}, |
|||
{"smlsd" , 0 , 6 , 0}, |
|||
{"smlsld" , 0 , 6 , 0}, |
|||
{"smmla" , 0 , 6 , 0}, |
|||
{"smmls" , 0 , 6 , 0}, |
|||
{"smlald" , 0 , 6 , 0}, |
|||
{"smlad" , 0 , 6 , 0}, |
|||
{"smlaw" , 0 , 4 , 0}, |
|||
{"smulw" , 0 , 4 , 0}, |
|||
{"pkhtb" , 0 , 6 , 0}, |
|||
{"pkhbt" , 0 , 6 , 0}, |
|||
{"smul" , 0 , 4 , 0}, |
|||
{"smlal" , 0 , 4 , 0}, |
|||
{"smla" , 0 , 4 , 0}, |
|||
{"mcrr" , 0 , 6 , 0}, |
|||
{"mrrc" , 0 , 6 , 0}, |
|||
{"cmp" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000}, |
|||
{"tst" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000}, |
|||
{"teq" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000}, |
|||
{"cmn" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000}, |
|||
{"smull" , 0 , 0 , 0}, |
|||
{"umull" , 0 , 0 , 0}, |
|||
{"umlal" , 0 , 0 , 0}, |
|||
{"smlal" , 0 , 0 , 0}, |
|||
{"mul" , 0 , 0 , 0}, |
|||
{"mla" , 0 , 0 , 0}, |
|||
{"ssat" , 0 , 6 , 0}, |
|||
{"usat" , 0 , 6 , 0}, |
|||
{"mrs" , 0 , 0 , 0}, |
|||
{"msr" , 0 , 0 , 0}, |
|||
{"and" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000}, |
|||
{"bic" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000}, |
|||
{"ldm" , 0 , 0 , 0}, |
|||
{"eor" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000}, |
|||
{"add" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000}, |
|||
{"rsb" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000}, |
|||
{"rsc" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000}, |
|||
{"sbc" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000}, |
|||
{"adc" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000}, |
|||
{"sub" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000}, |
|||
{"orr" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000}, |
|||
{"mvn" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000}, |
|||
{"mov" , 3 , 0 , 4, 4, 0x00000001, 7, 7, 0x00000001, 25, 25, 0x00000000}, |
|||
{"stm" , 0 , 0 , 0}, |
|||
{"ldm" , 0 , 0 , 0}, |
|||
{"ldrsh" , 0 , 2 , 0}, |
|||
{"stm" , 0 , 0 , 0}, |
|||
{"ldm" , 0 , 0 , 0}, |
|||
{"ldrsb" , 0 , 2 , 0}, |
|||
{"strd" , 0 , 4 , 0}, |
|||
{"ldrh" , 0 , 0 , 0}, |
|||
{"strh" , 0 , 0 , 0}, |
|||
{"ldrd" , 0 , 4 , 0}, |
|||
{"strt" , 0 , 0 , 0}, |
|||
{"strbt" , 0 , 0 , 0}, |
|||
{"ldrbt" , 0 , 0 , 0}, |
|||
{"ldrt" , 0 , 0 , 0}, |
|||
{"mrc" , 0 , 6 , 0}, |
|||
{"mcr" , 0 , 0 , 0}, |
|||
{"msr" , 0 , 0 , 0}, |
|||
{"ldrb" , 0 , 0 , 0}, |
|||
{"strb" , 0 , 0 , 0}, |
|||
{"ldr" , 0 , 0 , 0}, |
|||
{"ldrcond" , 1 , 0 , 28, 31, 0x0000000e}, |
|||
{"str" , 0 , 0 , 0}, |
|||
{"cdp" , 0 , 0 , 0}, |
|||
{"stc" , 0 , 0 , 0}, |
|||
{"ldc" , 0 , 0 , 0}, |
|||
{"swi" , 0 , 0 , 0}, |
|||
{"bbl" , 0 , 0 , 0}, |
|||
{"bl_1_thumb", 0, INVALID, 0},/* should be table[-4] */ |
|||
{"bl_2_thumb", 0, INVALID, 0}, /* should be located at the end of the table[-3] */ |
|||
{"blx_1_thumb", 0, INVALID, 0}, /* should be located at table[-2] */ |
|||
{"invalid", 0, INVALID, 0} |
|||
}; |
|||
|
|||
int decode_arm_instr(uint32_t instr, int32_t *idx) |
|||
{ |
|||
int n = 0; |
|||
int base = 0; |
|||
int ret = DECODE_FAILURE; |
|||
int i = 0; |
|||
int instr_slots = sizeof(arm_instruction)/sizeof(ISEITEM); |
|||
for (i = 0; i < instr_slots; i++) |
|||
{ |
|||
// ret = DECODE_SUCCESS;
|
|||
n = arm_instruction[i].attribute_value; |
|||
base = 0; |
|||
while (n) { |
|||
if (arm_instruction[i].content[base + 1] == 31 && arm_instruction[i].content[base] == 0) { |
|||
/* clrex */ |
|||
if (instr != arm_instruction[i].content[base + 2]) { |
|||
break; |
|||
} |
|||
} else if (BITS(arm_instruction[i].content[base], arm_instruction[i].content[base + 1]) != arm_instruction[i].content[base + 2]) { |
|||
break; |
|||
} |
|||
base += 3; |
|||
n --; |
|||
} |
|||
//All conditions is satisfied.
|
|||
if (n == 0) |
|||
ret = DECODE_SUCCESS; |
|||
|
|||
if (ret == DECODE_SUCCESS) { |
|||
n = arm_exclusion_code[i].attribute_value; |
|||
if (n != 0) { |
|||
base = 0; |
|||
while (n) { |
|||
if (BITS(arm_exclusion_code[i].content[base], arm_exclusion_code[i].content[base + 1]) != arm_exclusion_code[i].content[base + 2]) { |
|||
break; } |
|||
base += 3; |
|||
n --; |
|||
} |
|||
//All conditions is satisfied.
|
|||
if (n == 0) |
|||
ret = DECODE_FAILURE; |
|||
} |
|||
} |
|||
|
|||
if (ret == DECODE_SUCCESS) { |
|||
*idx = i; |
|||
return ret; |
|||
} |
|||
} |
|||
return ret; |
|||
} |
|||
|
|||
@ -0,0 +1,155 @@ |
|||
/* Copyright (C) |
|||
* 2012 - Michael.Kang blackfin.kang@gmail.com |
|||
* This program is free software; you can redistribute it and/or |
|||
* modify it under the terms of the GNU General Public License |
|||
* as published by the Free Software Foundation; either version 2 |
|||
* of the License, or (at your option) any later version. |
|||
* |
|||
* This program is distributed in the hope that it will be useful, |
|||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|||
* GNU General Public License for more details. |
|||
* |
|||
* You should have received a copy of the GNU General Public License |
|||
* along with this program; if not, write to the Free Software |
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
|||
* |
|||
*/ |
|||
|
|||
/** |
|||
* @file arm_dyncom_dec.h |
|||
* @brief Some common utility for arm instruction decoder |
|||
* @author Michael.Kang blackfin.kang@gmail.com |
|||
* @version 7849 |
|||
* @date 2012-03-15 |
|||
*/ |
|||
|
|||
#ifndef __ARM_DYNCOM_DEC__ |
|||
#define __ARM_DYNCOM_DEC__ |
|||
|
|||
#define BITS(a,b) ((instr >> (a)) & ((1 << (1+(b)-(a)))-1)) |
|||
#define BIT(n) ((instr >> (n)) & 1) |
|||
#define BAD do{printf("meet BAD at %s, instr is %x\n", __FUNCTION__, instr ); /*exit(0);*/}while(0); |
|||
#define ptr_N cpu->ptr_N |
|||
#define ptr_Z cpu->ptr_Z |
|||
#define ptr_C cpu->ptr_C |
|||
#define ptr_V cpu->ptr_V |
|||
#define ptr_I cpu->ptr_I |
|||
#define ptr_T cpu->ptr_T |
|||
#define ptr_CPSR cpu->ptr_gpr[16] |
|||
|
|||
/* for MUL instructions */ |
|||
/*xxxx xxxx xxxx 1111 xxxx xxxx xxxx xxxx */ |
|||
#define RDHi ((instr >> 16) & 0xF) |
|||
/*xxxx xxxx xxxx xxxx 1111 xxxx xxxx xxxx */ |
|||
#define RDLo ((instr >> 12) & 0xF) |
|||
/*xxxx xxxx xxxx 1111 xxxx xxxx xxxx xxxx */ |
|||
#define MUL_RD ((instr >> 16) & 0xF) |
|||
/*xxxx xxxx xxxx xxxx 1111 xxxx xxxx xxxx */ |
|||
#define MUL_RN ((instr >> 12) & 0xF) |
|||
/*xxxx xxxx xxxx xxxx xxxx 1111 xxxx xxxx */ |
|||
#define RS ((instr >> 8) & 0xF) |
|||
|
|||
/*xxxx xxxx xxxx xxxx 1111 xxxx xxxx xxxx */ |
|||
#define RD ((instr >> 12) & 0xF) |
|||
/*xxxx xxxx xxxx 1111 xxxx xxxx xxxx xxxx */ |
|||
#define RN ((instr >> 16) & 0xF) |
|||
/*xxxx xxxx xxxx xxxx xxxx xxxx xxxx 1111 */ |
|||
#define RM (instr & 0xF) |
|||
#define BIT(n) ((instr >> (n)) & 1) |
|||
#define BITS(a,b) ((instr >> (a)) & ((1 << (1+(b)-(a)))-1)) |
|||
|
|||
/* CP15 registers */ |
|||
#define OPCODE_1 BITS(21, 23) |
|||
#define CRn BITS(16, 19) |
|||
#define CRm BITS(0, 3) |
|||
#define OPCODE_2 BITS(5, 7) |
|||
|
|||
/*xxxx xx1x xxxx xxxx xxxx xxxx xxxx xxxx */ |
|||
#define I BIT(25) |
|||
/*xxxx xxxx xxx1 xxxx xxxx xxxx xxxx xxxx */ |
|||
#define S BIT(20) |
|||
|
|||
#define SHIFT BITS(5,6) |
|||
#define SHIFT_IMM BITS(7,11) |
|||
#define IMMH BITS(8,11) |
|||
#define IMML BITS(0,3) |
|||
|
|||
#define LSPBIT BIT(24) |
|||
#define LSUBIT BIT(23) |
|||
#define LSBBIT BIT(22) |
|||
#define LSWBIT BIT(21) |
|||
#define LSLBIT BIT(20) |
|||
#define LSSHBITS BITS(5,6) |
|||
#define OFFSET12 BITS(0,11) |
|||
#define SBIT BIT(20) |
|||
#define DESTReg (BITS (12, 15)) |
|||
|
|||
/* they are in unused state, give a corrent value when using */ |
|||
#define IS_V5E 0 |
|||
#define IS_V5 0 |
|||
#define IS_V6 0 |
|||
#define LHSReg 0 |
|||
|
|||
/* temp define the using the pc reg need implement a flow */ |
|||
#define STORE_CHECK_RD_PC ADD(R(RD), CONST(INSTR_SIZE * 2)) |
|||
|
|||
#define OPERAND operand(cpu,instr,bb,NULL) |
|||
#define SCO_OPERAND(sco) operand(cpu,instr,bb,sco) |
|||
#define BOPERAND boperand(instr) |
|||
|
|||
#define CHECK_RN_PC (RN==15? ADD(AND(R(RN), CONST(~0x1)), CONST(INSTR_SIZE * 2)):R(RN)) |
|||
#define CHECK_RN_PC_WA (RN==15? ADD(AND(R(RN), CONST(~0x3)), CONST(INSTR_SIZE * 2)):R(RN)) |
|||
|
|||
#define GET_USER_MODE() (OR(ICMP_EQ(R(MODE_REG), CONST(USER32MODE)), ICMP_EQ(R(MODE_REG), CONST(SYSTEM32MODE)))) |
|||
|
|||
int decode_arm_instr(uint32_t instr, int32_t *idx); |
|||
|
|||
enum DECODE_STATUS { |
|||
DECODE_SUCCESS, |
|||
DECODE_FAILURE |
|||
}; |
|||
|
|||
struct instruction_set_encoding_item { |
|||
const char *name; |
|||
int attribute_value; |
|||
int version; |
|||
u32 content[21]; |
|||
}; |
|||
|
|||
typedef struct instruction_set_encoding_item ISEITEM; |
|||
|
|||
#define RECORD_WB(value, flag) {cpu->dyncom_engine->wb_value = value;cpu->dyncom_engine->wb_flag = flag;} |
|||
#define INIT_WB(wb_value, wb_flag) RECORD_WB(wb_value, wb_flag) |
|||
|
|||
#define EXECUTE_WB(base_reg) {if(cpu->dyncom_engine->wb_flag) \ |
|||
LET(base_reg, cpu->dyncom_engine->wb_value);} |
|||
inline int get_reg_count(uint32_t instr){ |
|||
int i = BITS(0,15); |
|||
int count = 0; |
|||
while(i){ |
|||
if(i & 1) |
|||
count ++; |
|||
i = i >> 1; |
|||
} |
|||
return count; |
|||
} |
|||
|
|||
enum ARMVER { |
|||
INVALID = 0, |
|||
ARMALL, |
|||
ARMV4, |
|||
ARMV4T, |
|||
ARMV5T, |
|||
ARMV5TE, |
|||
ARMV5TEJ, |
|||
ARMV6, |
|||
ARM1176JZF_S, |
|||
ARMVFP2, |
|||
ARMVFP3 |
|||
}; |
|||
|
|||
//extern const INSTRACT arm_instruction_action[]; |
|||
extern const ISEITEM arm_instruction[]; |
|||
|
|||
#endif |
|||
6559
src/core/arm/dyncom/arm_dyncom_interpreter.cpp
File diff suppressed because it is too large
View File
File diff suppressed because it is too large
View File
@ -0,0 +1,7 @@ |
|||
// Copyright 2014 Citra Emulator Project |
|||
// Licensed under GPLv2 |
|||
// Refer to the license.txt file included. |
|||
|
|||
#pragma once |
|||
|
|||
void InterpreterMainLoop(ARMul_State* state); |
|||
@ -0,0 +1,120 @@ |
|||
/* Copyright (C)
|
|||
* 2011 - Michael.Kang blackfin.kang@gmail.com |
|||
* This program is free software; you can redistribute it and/or |
|||
* modify it under the terms of the GNU General Public License |
|||
* as published by the Free Software Foundation; either version 2 |
|||
* of the License, or (at your option) any later version. |
|||
* |
|||
* This program is distributed in the hope that it will be useful, |
|||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|||
* GNU General Public License for more details. |
|||
* |
|||
* You should have received a copy of the GNU General Public License |
|||
* along with this program; if not, write to the Free Software |
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
|||
* |
|||
*/ |
|||
/**
|
|||
* @file arm_dyncom_run.cpp |
|||
* @brief The dyncom run implementation for arm |
|||
* @author Michael.Kang blackfin.kang@gmail.com |
|||
* @version 78.77 |
|||
* @date 2011-11-20 |
|||
*/ |
|||
|
|||
#include <assert.h>
|
|||
|
|||
#include "core/arm/skyeye_common/armdefs.h"
|
|||
|
|||
void switch_mode(arm_core_t *core, uint32_t mode) |
|||
{ |
|||
uint32_t tmp1, tmp2; |
|||
if (core->Mode == mode) { |
|||
//Mode not changed.
|
|||
//printf("mode not changed\n");
|
|||
return; |
|||
} |
|||
//printf("%d --->>> %d\n", core->Mode, mode);
|
|||
//printf("In %s, Cpsr=0x%x, R15=0x%x, last_pc=0x%x, cpsr=0x%x, spsr_copy=0x%x, icounter=%lld\n", __FUNCTION__, core->Cpsr, core->Reg[15], core->last_pc, core->Cpsr, core->Spsr_copy, core->icounter);
|
|||
if (mode != USERBANK) { |
|||
switch (core->Mode) { |
|||
case USER32MODE: |
|||
core->Reg_usr[0] = core->Reg[13]; |
|||
core->Reg_usr[1] = core->Reg[14]; |
|||
break; |
|||
case IRQ32MODE: |
|||
core->Reg_irq[0] = core->Reg[13]; |
|||
core->Reg_irq[1] = core->Reg[14]; |
|||
core->Spsr[IRQBANK] = core->Spsr_copy; |
|||
break; |
|||
case SVC32MODE: |
|||
core->Reg_svc[0] = core->Reg[13]; |
|||
core->Reg_svc[1] = core->Reg[14]; |
|||
core->Spsr[SVCBANK] = core->Spsr_copy; |
|||
break; |
|||
case ABORT32MODE: |
|||
core->Reg_abort[0] = core->Reg[13]; |
|||
core->Reg_abort[1] = core->Reg[14]; |
|||
core->Spsr[ABORTBANK] = core->Spsr_copy; |
|||
break; |
|||
case UNDEF32MODE: |
|||
core->Reg_undef[0] = core->Reg[13]; |
|||
core->Reg_undef[1] = core->Reg[14]; |
|||
core->Spsr[UNDEFBANK] = core->Spsr_copy; |
|||
break; |
|||
case FIQ32MODE: |
|||
core->Reg_firq[0] = core->Reg[13]; |
|||
core->Reg_firq[1] = core->Reg[14]; |
|||
core->Spsr[FIQBANK] = core->Spsr_copy; |
|||
break; |
|||
|
|||
} |
|||
|
|||
switch (mode) { |
|||
case USER32MODE: |
|||
core->Reg[13] = core->Reg_usr[0]; |
|||
core->Reg[14] = core->Reg_usr[1]; |
|||
core->Bank = USERBANK; |
|||
break; |
|||
case IRQ32MODE: |
|||
core->Reg[13] = core->Reg_irq[0]; |
|||
core->Reg[14] = core->Reg_irq[1]; |
|||
core->Spsr_copy = core->Spsr[IRQBANK]; |
|||
core->Bank = IRQBANK; |
|||
break; |
|||
case SVC32MODE: |
|||
core->Reg[13] = core->Reg_svc[0]; |
|||
core->Reg[14] = core->Reg_svc[1]; |
|||
core->Spsr_copy = core->Spsr[SVCBANK]; |
|||
core->Bank = SVCBANK; |
|||
break; |
|||
case ABORT32MODE: |
|||
core->Reg[13] = core->Reg_abort[0]; |
|||
core->Reg[14] = core->Reg_abort[1]; |
|||
core->Spsr_copy = core->Spsr[ABORTBANK]; |
|||
core->Bank = ABORTBANK; |
|||
break; |
|||
case UNDEF32MODE: |
|||
core->Reg[13] = core->Reg_undef[0]; |
|||
core->Reg[14] = core->Reg_undef[1]; |
|||
core->Spsr_copy = core->Spsr[UNDEFBANK]; |
|||
core->Bank = UNDEFBANK; |
|||
break; |
|||
case FIQ32MODE: |
|||
core->Reg[13] = core->Reg_firq[0]; |
|||
core->Reg[14] = core->Reg_firq[1]; |
|||
core->Spsr_copy = core->Spsr[FIQBANK]; |
|||
core->Bank = FIQBANK; |
|||
break; |
|||
|
|||
} |
|||
core->Mode = mode; |
|||
//printf("In %si end, Cpsr=0x%x, R15=0x%x, last_pc=0x%x, cpsr=0x%x, spsr_copy=0x%x, icounter=%lld\n", __FUNCTION__, core->Cpsr, core->Reg[15], core->last_pc, core->Cpsr, core->Spsr_copy, core->icounter);
|
|||
//printf("\n--------------------------------------\n");
|
|||
} |
|||
else { |
|||
printf("user mode\n"); |
|||
exit(-2); |
|||
} |
|||
} |
|||
@ -0,0 +1,55 @@ |
|||
/* Copyright (C) |
|||
* 2011 - Michael.Kang blackfin.kang@gmail.com |
|||
* This program is free software; you can redistribute it and/or |
|||
* modify it under the terms of the GNU General Public License |
|||
* as published by the Free Software Foundation; either version 2 |
|||
* of the License, or (at your option) any later version. |
|||
* |
|||
* This program is distributed in the hope that it will be useful, |
|||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|||
* GNU General Public License for more details. |
|||
* |
|||
* You should have received a copy of the GNU General Public License |
|||
* along with this program; if not, write to the Free Software |
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
|||
* |
|||
*/ |
|||
|
|||
#ifndef __ARM_DYNCOM_RUN__ |
|||
#define __ARM_DYNCOM_RUN__ |
|||
|
|||
#include "core/arm/skyeye_common/skyeye_types.h" |
|||
|
|||
void switch_mode(arm_core_t *core, uint32_t mode); |
|||
|
|||
/* FIXME, we temporarily think thumb instruction is always 16 bit */ |
|||
static inline uint32 GET_INST_SIZE(arm_core_t* core){ |
|||
return core->TFlag? 2 : 4; |
|||
} |
|||
|
|||
/** |
|||
* @brief Read R15 and forced R15 to wold align, used address calculation |
|||
* |
|||
* @param core |
|||
* @param Rn |
|||
* |
|||
* @return |
|||
*/ |
|||
static inline addr_t CHECK_READ_REG15_WA(arm_core_t* core, int Rn){ |
|||
return (Rn == 15)? ((core->Reg[15] & ~0x3) + GET_INST_SIZE(core) * 2) : core->Reg[Rn]; |
|||
} |
|||
|
|||
/** |
|||
* @brief Read R15, used to data processing with pc |
|||
* |
|||
* @param core |
|||
* @param Rn |
|||
* |
|||
* @return |
|||
*/ |
|||
static inline uint32 CHECK_READ_REG15(arm_core_t* core, int Rn){ |
|||
return (Rn == 15)? ((core->Reg[15] & ~0x1) + GET_INST_SIZE(core) * 2) : core->Reg[Rn]; |
|||
} |
|||
|
|||
#endif |
|||
@ -0,0 +1,521 @@ |
|||
/* Copyright (C)
|
|||
* 2011 - Michael.Kang blackfin.kang@gmail.com |
|||
* This program is free software; you can redistribute it and/or |
|||
* modify it under the terms of the GNU General Public License |
|||
* as published by the Free Software Foundation; either version 2 |
|||
* of the License, or (at your option) any later version. |
|||
* |
|||
* This program is distributed in the hope that it will be useful, |
|||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|||
* GNU General Public License for more details. |
|||
* |
|||
* You should have received a copy of the GNU General Public License |
|||
* along with this program; if not, write to the Free Software |
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
|||
* |
|||
*/ |
|||
/**
|
|||
* @file arm_dyncom_thumb.c |
|||
* @brief The thumb dynamic interpreter |
|||
* @author Michael.Kang blackfin.kang@gmail.com |
|||
* @version 78.77 |
|||
* @date 2011-11-07 |
|||
*/ |
|||
|
|||
/* We can provide simple Thumb simulation by decoding the Thumb
|
|||
instruction into its corresponding ARM instruction, and using the |
|||
existing ARM simulator. */ |
|||
|
|||
#include "core/arm/skyeye_common/skyeye_defs.h"
|
|||
|
|||
#ifndef MODET /* required for the Thumb instruction support */
|
|||
#if 1
|
|||
#error "MODET needs to be defined for the Thumb world to work"
|
|||
#else
|
|||
#define MODET (1)
|
|||
#endif
|
|||
#endif
|
|||
|
|||
#include "core/arm/skyeye_common/armos.h"
|
|||
#include "core/arm/dyncom/arm_dyncom_thumb.h"
|
|||
|
|||
/* Decode a 16bit Thumb instruction. The instruction is in the low
|
|||
16-bits of the tinstr field, with the following Thumb instruction |
|||
held in the high 16-bits. Passing in two Thumb instructions allows |
|||
easier simulation of the special dual BL instruction. */ |
|||
|
|||
tdstate thumb_translate (addr_t addr, uint32_t instr, uint32_t* ainstr, uint32_t* inst_size) |
|||
{ |
|||
tdstate valid = t_uninitialized; |
|||
ARMword next_instr; |
|||
ARMword tinstr; |
|||
tinstr = instr; |
|||
/* The endian should be judge here */ |
|||
#if 0
|
|||
if (state->bigendSig) { |
|||
next_instr = tinstr & 0xFFFF; |
|||
tinstr >>= 16; |
|||
} |
|||
else { |
|||
next_instr = tinstr >> 16; |
|||
tinstr &= 0xFFFF; |
|||
} |
|||
#endif
|
|||
if((addr & 0x3) != 0) |
|||
tinstr = instr >> 16; |
|||
else |
|||
tinstr &= 0xFFFF; |
|||
|
|||
//printf("In %s, instr=0x%x, tinstr=0x%x, r15=0x%x\n", __FUNCTION__, instr, tinstr, cpu->translate_pc);
|
|||
#if 1 /* debugging to catch non updates */
|
|||
*ainstr = 0xDEADC0DE; |
|||
#endif
|
|||
|
|||
switch ((tinstr & 0xF800) >> 11) { |
|||
case 0: /* LSL */ |
|||
case 1: /* LSR */ |
|||
case 2: /* ASR */ |
|||
/* Format 1 */ |
|||
*ainstr = 0xE1B00000 /* base opcode */ |
|||
| ((tinstr & 0x1800) >> (11 - 5)) /* shift type */ |
|||
|((tinstr & 0x07C0) << (7 - 6)) /* imm5 */ |
|||
|((tinstr & 0x0038) >> 3) /* Rs */ |
|||
|((tinstr & 0x0007) << 12); /* Rd */ |
|||
break; |
|||
case 3: /* ADD/SUB */ |
|||
/* Format 2 */ |
|||
{ |
|||
ARMword subset[4] = { |
|||
0xE0900000, /* ADDS Rd,Rs,Rn */ |
|||
0xE0500000, /* SUBS Rd,Rs,Rn */ |
|||
0xE2900000, /* ADDS Rd,Rs,#imm3 */ |
|||
0xE2500000 /* SUBS Rd,Rs,#imm3 */ |
|||
}; |
|||
/* It is quicker indexing into a table, than performing switch
|
|||
or conditionals: */ |
|||
*ainstr = subset[(tinstr & 0x0600) >> 9] /* base opcode */ |
|||
|((tinstr & 0x01C0) >> 6) /* Rn or imm3 */ |
|||
|((tinstr & 0x0038) << (16 - 3)) /* Rs */ |
|||
|((tinstr & 0x0007) << (12 - 0)); /* Rd */ |
|||
} |
|||
break; |
|||
case 4: /* MOV */ |
|||
case 5: /* CMP */ |
|||
case 6: /* ADD */ |
|||
case 7: /* SUB */ |
|||
/* Format 3 */ |
|||
{ |
|||
ARMword subset[4] = { |
|||
0xE3B00000, /* MOVS Rd,#imm8 */ |
|||
0xE3500000, /* CMP Rd,#imm8 */ |
|||
0xE2900000, /* ADDS Rd,Rd,#imm8 */ |
|||
0xE2500000, /* SUBS Rd,Rd,#imm8 */ |
|||
}; |
|||
*ainstr = subset[(tinstr & 0x1800) >> 11] /* base opcode */ |
|||
|((tinstr & 0x00FF) >> 0) /* imm8 */ |
|||
|((tinstr & 0x0700) << (16 - 8)) /* Rn */ |
|||
|((tinstr & 0x0700) << (12 - 8)); /* Rd */ |
|||
} |
|||
break; |
|||
case 8: /* Arithmetic and high register transfers */ |
|||
/* TODO: Since the subsets for both Format 4 and Format 5
|
|||
instructions are made up of different ARM encodings, we could |
|||
save the following conditional, and just have one large |
|||
subset. */ |
|||
if ((tinstr & (1 << 10)) == 0) { |
|||
typedef enum |
|||
{ t_norm, t_shift, t_neg, t_mul }otype_t; |
|||
|
|||
/* Format 4 */ |
|||
struct |
|||
{ |
|||
ARMword opcode; |
|||
otype_t otype; |
|||
} |
|||
subset[16] = { |
|||
{ |
|||
0xE0100000, t_norm}, /* ANDS Rd,Rd,Rs */ |
|||
{ |
|||
0xE0300000, t_norm}, /* EORS Rd,Rd,Rs */ |
|||
{ |
|||
0xE1B00010, t_shift}, /* MOVS Rd,Rd,LSL Rs */ |
|||
{ |
|||
0xE1B00030, t_shift}, /* MOVS Rd,Rd,LSR Rs */ |
|||
{ |
|||
0xE1B00050, t_shift}, /* MOVS Rd,Rd,ASR Rs */ |
|||
{ |
|||
0xE0B00000, t_norm}, /* ADCS Rd,Rd,Rs */ |
|||
{ |
|||
0xE0D00000, t_norm}, /* SBCS Rd,Rd,Rs */ |
|||
{ |
|||
0xE1B00070, t_shift}, /* MOVS Rd,Rd,ROR Rs */ |
|||
{ |
|||
0xE1100000, t_norm}, /* TST Rd,Rs */ |
|||
{ |
|||
0xE2700000, t_neg}, /* RSBS Rd,Rs,#0 */ |
|||
{ |
|||
0xE1500000, t_norm}, /* CMP Rd,Rs */ |
|||
{ |
|||
0xE1700000, t_norm}, /* CMN Rd,Rs */ |
|||
{ |
|||
0xE1900000, t_norm}, /* ORRS Rd,Rd,Rs */ |
|||
{ |
|||
0xE0100090, t_mul}, /* MULS Rd,Rd,Rs */ |
|||
{ |
|||
0xE1D00000, t_norm}, /* BICS Rd,Rd,Rs */ |
|||
{ |
|||
0xE1F00000, t_norm} /* MVNS Rd,Rs */ |
|||
}; |
|||
*ainstr = subset[(tinstr & 0x03C0) >> 6].opcode; /* base */ |
|||
switch (subset[(tinstr & 0x03C0) >> 6].otype) { |
|||
case t_norm: |
|||
*ainstr |= ((tinstr & 0x0007) << 16) /* Rn */ |
|||
|((tinstr & 0x0007) << 12) /* Rd */ |
|||
|((tinstr & 0x0038) >> 3); /* Rs */ |
|||
break; |
|||
case t_shift: |
|||
*ainstr |= ((tinstr & 0x0007) << 12) /* Rd */ |
|||
|((tinstr & 0x0007) >> 0) /* Rm */ |
|||
|((tinstr & 0x0038) << (8 - 3)); /* Rs */ |
|||
break; |
|||
case t_neg: |
|||
*ainstr |= ((tinstr & 0x0007) << 12) /* Rd */ |
|||
|((tinstr & 0x0038) << (16 - 3)); /* Rn */ |
|||
break; |
|||
case t_mul: |
|||
*ainstr |= ((tinstr & 0x0007) << 16) /* Rd */ |
|||
|((tinstr & 0x0007) << 8) /* Rs */ |
|||
|((tinstr & 0x0038) >> 3); /* Rm */ |
|||
break; |
|||
} |
|||
} |
|||
else { |
|||
/* Format 5 */ |
|||
ARMword Rd = ((tinstr & 0x0007) >> 0); |
|||
ARMword Rs = ((tinstr & 0x0038) >> 3); |
|||
if (tinstr & (1 << 7)) |
|||
Rd += 8; |
|||
if (tinstr & (1 << 6)) |
|||
Rs += 8; |
|||
switch ((tinstr & 0x03C0) >> 6) { |
|||
case 0x1: /* ADD Rd,Rd,Hs */ |
|||
case 0x2: /* ADD Hd,Hd,Rs */ |
|||
case 0x3: /* ADD Hd,Hd,Hs */ |
|||
*ainstr = 0xE0800000 /* base */ |
|||
| (Rd << 16) /* Rn */ |
|||
|(Rd << 12) /* Rd */ |
|||
|(Rs << 0); /* Rm */ |
|||
break; |
|||
case 0x5: /* CMP Rd,Hs */ |
|||
case 0x6: /* CMP Hd,Rs */ |
|||
case 0x7: /* CMP Hd,Hs */ |
|||
*ainstr = 0xE1500000 /* base */ |
|||
| (Rd << 16) /* Rn */ |
|||
|(Rd << 12) /* Rd */ |
|||
|(Rs << 0); /* Rm */ |
|||
break; |
|||
case 0x9: /* MOV Rd,Hs */ |
|||
case 0xA: /* MOV Hd,Rs */ |
|||
case 0xB: /* MOV Hd,Hs */ |
|||
*ainstr = 0xE1A00000 /* base */ |
|||
| (Rd << 16) /* Rn */ |
|||
|(Rd << 12) /* Rd */ |
|||
|(Rs << 0); /* Rm */ |
|||
break; |
|||
case 0xC: /* BX Rs */ |
|||
case 0xD: /* BX Hs */ |
|||
*ainstr = 0xE12FFF10 /* base */ |
|||
| ((tinstr & 0x0078) >> 3); /* Rd */ |
|||
break; |
|||
case 0x0: /* UNDEFINED */ |
|||
case 0x4: /* UNDEFINED */ |
|||
case 0x8: /* UNDEFINED */ |
|||
valid = t_undefined; |
|||
break; |
|||
case 0xE: /* BLX */ |
|||
case 0xF: /* BLX */ |
|||
|
|||
//if (state->is_v5) {
|
|||
if(1){ |
|||
//valid = t_branch;
|
|||
#if 1
|
|||
*ainstr = 0xE1200030 /* base */ |
|||
|(Rs << 0); /* Rm */ |
|||
#endif
|
|||
} else { |
|||
valid = t_undefined; |
|||
} |
|||
break; |
|||
} |
|||
} |
|||
break; |
|||
case 9: /* LDR Rd,[PC,#imm8] */ |
|||
/* Format 6 */ |
|||
*ainstr = 0xE59F0000 /* base */ |
|||
| ((tinstr & 0x0700) << (12 - 8)) /* Rd */ |
|||
|((tinstr & 0x00FF) << (2 - 0)); /* off8 */ |
|||
break; |
|||
case 10: |
|||
case 11: |
|||
/* TODO: Format 7 and Format 8 perform the same ARM encoding, so
|
|||
the following could be merged into a single subset, saving on |
|||
the following boolean: */ |
|||
if ((tinstr & (1 << 9)) == 0) { |
|||
/* Format 7 */ |
|||
ARMword subset[4] = { |
|||
0xE7800000, /* STR Rd,[Rb,Ro] */ |
|||
0xE7C00000, /* STRB Rd,[Rb,Ro] */ |
|||
0xE7900000, /* LDR Rd,[Rb,Ro] */ |
|||
0xE7D00000 /* LDRB Rd,[Rb,Ro] */ |
|||
}; |
|||
*ainstr = subset[(tinstr & 0x0C00) >> 10] /* base */ |
|||
|((tinstr & 0x0007) << (12 - 0)) /* Rd */ |
|||
|((tinstr & 0x0038) << (16 - 3)) /* Rb */ |
|||
|((tinstr & 0x01C0) >> 6); /* Ro */ |
|||
} |
|||
else { |
|||
/* Format 8 */ |
|||
ARMword subset[4] = { |
|||
0xE18000B0, /* STRH Rd,[Rb,Ro] */ |
|||
0xE19000D0, /* LDRSB Rd,[Rb,Ro] */ |
|||
0xE19000B0, /* LDRH Rd,[Rb,Ro] */ |
|||
0xE19000F0 /* LDRSH Rd,[Rb,Ro] */ |
|||
}; |
|||
*ainstr = subset[(tinstr & 0x0C00) >> 10] /* base */ |
|||
|((tinstr & 0x0007) << (12 - 0)) /* Rd */ |
|||
|((tinstr & 0x0038) << (16 - 3)) /* Rb */ |
|||
|((tinstr & 0x01C0) >> 6); /* Ro */ |
|||
} |
|||
break; |
|||
case 12: /* STR Rd,[Rb,#imm5] */ |
|||
case 13: /* LDR Rd,[Rb,#imm5] */ |
|||
case 14: /* STRB Rd,[Rb,#imm5] */ |
|||
case 15: /* LDRB Rd,[Rb,#imm5] */ |
|||
/* Format 9 */ |
|||
{ |
|||
ARMword subset[4] = { |
|||
0xE5800000, /* STR Rd,[Rb,#imm5] */ |
|||
0xE5900000, /* LDR Rd,[Rb,#imm5] */ |
|||
0xE5C00000, /* STRB Rd,[Rb,#imm5] */ |
|||
0xE5D00000 /* LDRB Rd,[Rb,#imm5] */ |
|||
}; |
|||
/* The offset range defends on whether we are transferring a
|
|||
byte or word value: */ |
|||
*ainstr = subset[(tinstr & 0x1800) >> 11] /* base */ |
|||
|((tinstr & 0x0007) << (12 - 0)) /* Rd */ |
|||
|((tinstr & 0x0038) << (16 - 3)) /* Rb */ |
|||
|((tinstr & 0x07C0) >> (6 - ((tinstr & (1 << 12)) ? 0 : 2))); /* off5 */ |
|||
} |
|||
break; |
|||
case 16: /* STRH Rd,[Rb,#imm5] */ |
|||
case 17: /* LDRH Rd,[Rb,#imm5] */ |
|||
/* Format 10 */ |
|||
*ainstr = ((tinstr & (1 << 11)) /* base */ |
|||
? 0xE1D000B0 /* LDRH */ |
|||
: 0xE1C000B0) /* STRH */ |
|||
|((tinstr & 0x0007) << (12 - 0)) /* Rd */ |
|||
|((tinstr & 0x0038) << (16 - 3)) /* Rb */ |
|||
|((tinstr & 0x01C0) >> (6 - 1)) /* off5, low nibble */ |
|||
|((tinstr & 0x0600) >> (9 - 8)); /* off5, high nibble */ |
|||
break; |
|||
case 18: /* STR Rd,[SP,#imm8] */ |
|||
case 19: /* LDR Rd,[SP,#imm8] */ |
|||
/* Format 11 */ |
|||
*ainstr = ((tinstr & (1 << 11)) /* base */ |
|||
? 0xE59D0000 /* LDR */ |
|||
: 0xE58D0000) /* STR */ |
|||
|((tinstr & 0x0700) << (12 - 8)) /* Rd */ |
|||
|((tinstr & 0x00FF) << 2); /* off8 */ |
|||
break; |
|||
case 20: /* ADD Rd,PC,#imm8 */ |
|||
case 21: /* ADD Rd,SP,#imm8 */ |
|||
/* Format 12 */ |
|||
if ((tinstr & (1 << 11)) == 0) { |
|||
/* NOTE: The PC value used here should by word aligned */ |
|||
/* We encode shift-left-by-2 in the rotate immediate field,
|
|||
so no shift of off8 is needed. */ |
|||
*ainstr = 0xE28F0F00 /* base */ |
|||
| ((tinstr & 0x0700) << (12 - 8)) /* Rd */ |
|||
|(tinstr & 0x00FF); /* off8 */ |
|||
} |
|||
else { |
|||
/* We encode shift-left-by-2 in the rotate immediate field,
|
|||
so no shift of off8 is needed. */ |
|||
*ainstr = 0xE28D0F00 /* base */ |
|||
| ((tinstr & 0x0700) << (12 - 8)) /* Rd */ |
|||
|(tinstr & 0x00FF); /* off8 */ |
|||
} |
|||
break; |
|||
case 22: |
|||
case 23: |
|||
if ((tinstr & 0x0F00) == 0x0000) { |
|||
/* Format 13 */ |
|||
/* NOTE: The instruction contains a shift left of 2
|
|||
equivalent (implemented as ROR #30): */ |
|||
*ainstr = ((tinstr & (1 << 7)) /* base */ |
|||
? 0xE24DDF00 /* SUB */ |
|||
: 0xE28DDF00) /* ADD */ |
|||
|(tinstr & 0x007F); /* off7 */ |
|||
} |
|||
else if ((tinstr & 0x0F00) == 0x0e00) |
|||
*ainstr = 0xEF000000 | SWI_Breakpoint; |
|||
else { |
|||
/* Format 14 */ |
|||
ARMword subset[4] = { |
|||
0xE92D0000, /* STMDB sp!,{rlist} */ |
|||
0xE92D4000, /* STMDB sp!,{rlist,lr} */ |
|||
0xE8BD0000, /* LDMIA sp!,{rlist} */ |
|||
0xE8BD8000 /* LDMIA sp!,{rlist,pc} */ |
|||
}; |
|||
*ainstr = subset[((tinstr & (1 << 11)) >> 10) | ((tinstr & (1 << 8)) >> 8)] /* base */ |
|||
|(tinstr & 0x00FF); /* mask8 */ |
|||
} |
|||
break; |
|||
case 24: /* STMIA */ |
|||
case 25: /* LDMIA */ |
|||
/* Format 15 */ |
|||
*ainstr = ((tinstr & (1 << 11)) /* base */ |
|||
? 0xE8B00000 /* LDMIA */ |
|||
: 0xE8A00000) /* STMIA */ |
|||
|((tinstr & 0x0700) << (16 - 8)) /* Rb */ |
|||
|(tinstr & 0x00FF); /* mask8 */ |
|||
break; |
|||
case 26: /* Bcc */ |
|||
case 27: /* Bcc/SWI */ |
|||
if ((tinstr & 0x0F00) == 0x0F00) { |
|||
#if 0
|
|||
if (tinstr == (ARMul_ABORTWORD & 0xffff) && |
|||
state->AbortAddr == pc) { |
|||
*ainstr = ARMul_ABORTWORD; |
|||
break; |
|||
} |
|||
#endif
|
|||
/* Format 17 : SWI */ |
|||
*ainstr = 0xEF000000; |
|||
/* Breakpoint must be handled specially. */ |
|||
if ((tinstr & 0x00FF) == 0x18) |
|||
*ainstr |= ((tinstr & 0x00FF) << 16); |
|||
/* New breakpoint value. See gdb/arm-tdep.c */ |
|||
else if ((tinstr & 0x00FF) == 0xFE) |
|||
*ainstr |= SWI_Breakpoint; |
|||
else |
|||
*ainstr |= (tinstr & 0x00FF); |
|||
} |
|||
else if ((tinstr & 0x0F00) != 0x0E00) { |
|||
/* Format 16 */ |
|||
#if 0
|
|||
int doit = FALSE; |
|||
/* TODO: Since we are doing a switch here, we could just add
|
|||
the SWI and undefined instruction checks into this |
|||
switch to same on a couple of conditionals: */ |
|||
switch ((tinstr & 0x0F00) >> 8) { |
|||
case EQ: |
|||
doit = ZFLAG; |
|||
break; |
|||
case NE: |
|||
doit = !ZFLAG; |
|||
break; |
|||
case VS: |
|||
doit = VFLAG; |
|||
break; |
|||
case VC: |
|||
doit = !VFLAG; |
|||
break; |
|||
case MI: |
|||
doit = NFLAG; |
|||
break; |
|||
case PL: |
|||
doit = !NFLAG; |
|||
break; |
|||
case CS: |
|||
doit = CFLAG; |
|||
break; |
|||
case CC: |
|||
doit = !CFLAG; |
|||
break; |
|||
case HI: |
|||
doit = (CFLAG && !ZFLAG); |
|||
break; |
|||
case LS: |
|||
doit = (!CFLAG || ZFLAG); |
|||
break; |
|||
case GE: |
|||
doit = ((!NFLAG && !VFLAG) |
|||
|| (NFLAG && VFLAG)); |
|||
break; |
|||
case LT: |
|||
doit = ((NFLAG && !VFLAG) |
|||
|| (!NFLAG && VFLAG)); |
|||
break; |
|||
case GT: |
|||
doit = ((!NFLAG && !VFLAG && !ZFLAG) |
|||
|| (NFLAG && VFLAG && !ZFLAG)); |
|||
break; |
|||
case LE: |
|||
doit = ((NFLAG && !VFLAG) |
|||
|| (!NFLAG && VFLAG)) || ZFLAG; |
|||
break; |
|||
} |
|||
if (doit) { |
|||
state->Reg[15] = (pc + 4 |
|||
+ (((tinstr & 0x7F) << 1) |
|||
| ((tinstr & (1 << 7)) ? |
|||
0xFFFFFF00 : 0))); |
|||
FLUSHPIPE; |
|||
} |
|||
#endif
|
|||
valid = t_branch; |
|||
} |
|||
else /* UNDEFINED : cc=1110(AL) uses different format */ |
|||
valid = t_undefined; |
|||
break; |
|||
case 28: /* B */ |
|||
/* Format 18 */ |
|||
#if 0
|
|||
state->Reg[15] = (pc + 4 + (((tinstr & 0x3FF) << 1) |
|||
| ((tinstr & (1 << 10)) ? |
|||
0xFFFFF800 : 0))); |
|||
#endif
|
|||
//FLUSHPIPE;
|
|||
valid = t_branch; |
|||
break; |
|||
case 29: |
|||
if(tinstr & 0x1) |
|||
valid = t_undefined; |
|||
else{ |
|||
/* BLX 1 for armv5t and above */ |
|||
//printf("In %s, After BLX(1),LR=0x%x,PC=0x%x, offset=0x%x\n", __FUNCTION__, state->Reg[14], state->Reg[15], (tinstr &0x7FF) << 1);
|
|||
valid = t_branch; |
|||
} |
|||
break; |
|||
case 30: /* BL instruction 1 */ |
|||
/* Format 19 */ |
|||
/* There is no single ARM instruction equivalent for this Thumb
|
|||
instruction. To keep the simulation simple (from the user |
|||
perspective) we check if the following instruction is the |
|||
second half of this BL, and if it is we simulate it |
|||
immediately. */ |
|||
valid = t_branch; |
|||
break; |
|||
case 31: /* BL instruction 2 */ |
|||
/* Format 19 */ |
|||
/* There is no single ARM instruction equivalent for this
|
|||
instruction. Also, it should only ever be matched with the |
|||
fmt19 "BL instruction 1" instruction. However, we do allow |
|||
the simulation of it on its own, with undefined results if |
|||
r14 is not suitably initialised. */ |
|||
{ |
|||
#if 0
|
|||
ARMword tmp = (pc + 2); |
|||
state->Reg[15] = |
|||
(state->Reg[14] + ((tinstr & 0x07FF) << 1)); |
|||
state->Reg[14] = (tmp | 1); |
|||
#endif
|
|||
valid = t_branch; |
|||
} |
|||
break; |
|||
} |
|||
*inst_size = 2; |
|||
return valid; |
|||
} |
|||
@ -0,0 +1,51 @@ |
|||
/* Copyright (C) |
|||
* 2011 - Michael.Kang blackfin.kang@gmail.com |
|||
* This program is free software; you can redistribute it and/or |
|||
* modify it under the terms of the GNU General Public License |
|||
* as published by the Free Software Foundation; either version 2 |
|||
* of the License, or (at your option) any later version. |
|||
* |
|||
* This program is distributed in the hope that it will be useful, |
|||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|||
* GNU General Public License for more details. |
|||
* |
|||
* You should have received a copy of the GNU General Public License |
|||
* along with this program; if not, write to the Free Software |
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
|||
* |
|||
*/ |
|||
|
|||
/** |
|||
* @file arm_dyncom_thumb.h |
|||
* @brief The thumb dyncom |
|||
* @author Michael.Kang blackfin.kang@gmail.com |
|||
* @version 78.77 |
|||
* @date 2011-11-07 |
|||
*/ |
|||
|
|||
#ifndef __ARM_DYNCOM_THUMB_H__ |
|||
#define __ARM_DYNCOM_THUMB_H__ |
|||
|
|||
#include "core/arm/skyeye_common/armdefs.h" |
|||
#include "core/arm/skyeye_common/skyeye_types.h" |
|||
|
|||
enum tdstate { |
|||
t_undefined, // Undefined Thumb instruction |
|||
t_decoded, // Instruction decoded to ARM equivalent |
|||
t_branch, // Thumb branch (already processed) |
|||
t_uninitialized, |
|||
}; |
|||
|
|||
tdstate |
|||
thumb_translate(addr_t addr, uint32_t instr, uint32_t* ainstr, uint32_t* inst_size); |
|||
static inline uint32 get_thumb_instr(uint32 instr, addr_t pc){ |
|||
uint32 tinstr; |
|||
if ((pc & 0x3) != 0) |
|||
tinstr = instr >> 16; |
|||
else |
|||
tinstr = instr & 0xFFFF; |
|||
return tinstr; |
|||
} |
|||
|
|||
#endif |
|||
@ -0,0 +1,55 @@ |
|||
/* |
|||
skyeye_types.h - some data types definition for skyeye debugger |
|||
Copyright (C) 2003 Skyeye Develop Group |
|||
for help please send mail to <skyeye-developer@lists.sf.linuxforum.net> |
|||
|
|||
This program is free software; you can redistribute it and/or modify |
|||
it under the terms of the GNU General Public License as published by |
|||
the Free Software Foundation; either version 2 of the License, or |
|||
(at your option) any later version. |
|||
|
|||
This program is distributed in the hope that it will be useful, |
|||
but WITHOUT ANY WARRANTY; without even the implied warranty of |
|||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|||
GNU General Public License for more details. |
|||
|
|||
You should have received a copy of the GNU General Public License |
|||
along with this program; if not, write to the Free Software |
|||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|||
|
|||
*/ |
|||
/* |
|||
* 12/16/2006 Michael.Kang <blackfin.kang@gmail.com> |
|||
*/ |
|||
|
|||
#ifndef __SKYEYE_TYPES_H |
|||
#define __SKYEYE_TYPES_H |
|||
|
|||
#include <stdint.h> |
|||
|
|||
/*default machine word length */ |
|||
|
|||
#ifndef __BEOS__ |
|||
/* To avoid the type conflict with the qemu */ |
|||
#ifndef QEMU |
|||
typedef uint8_t uint8; |
|||
typedef uint16_t uint16; |
|||
typedef uint32_t uint32; |
|||
typedef uint64_t uint64; |
|||
|
|||
typedef int8_t sint8; |
|||
typedef int16_t sint16; |
|||
typedef int32_t sint32; |
|||
typedef int64_t sint64; |
|||
#endif |
|||
|
|||
typedef uint32_t address_t; |
|||
typedef uint32_t uinteger_t; |
|||
typedef int32_t integer_t; |
|||
|
|||
typedef uint32_t physical_address_t; |
|||
typedef uint32_t generic_address_t; |
|||
|
|||
#endif |
|||
|
|||
#endif |
|||
@ -1,20 +0,0 @@ |
|||
// Copyright 2014 Citra Emulator Project |
|||
// Licensed under GPLv2 |
|||
// Refer to the license.txt file included. |
|||
|
|||
#pragma once |
|||
|
|||
#include "common/common_types.h" |
|||
|
|||
namespace HLE { |
|||
|
|||
/// Coprocessor operations |
|||
enum CoprocessorOperation { |
|||
DATA_SYNCHRONIZATION_BARRIER = 0xE0, |
|||
CALL_GET_THREAD_COMMAND_BUFFER = 0xE1, |
|||
}; |
|||
|
|||
/// Call an MRC (move to ARM register from coprocessor) instruction in HLE |
|||
s32 CallMRC(u32 instruction); |
|||
|
|||
} // namespace |
|||
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