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@ -47,68 +47,38 @@ ARM_DynCom::ARM_DynCom() : ticks(0) { |
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ARM_DynCom::~ARM_DynCom() { |
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} |
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/**
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* Set the Program Counter to an address |
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* @param addr Address to set PC to |
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*/ |
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void ARM_DynCom::SetPC(u32 pc) { |
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state->pc = state->Reg[15] = pc; |
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} |
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/*
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* Get the current Program Counter |
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* @return Returns current PC |
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*/ |
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u32 ARM_DynCom::GetPC() const { |
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return state->Reg[15]; |
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} |
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/**
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* Get an ARM register |
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* @param index Register index (0-15) |
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* @return Returns the value in the register |
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*/ |
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u32 ARM_DynCom::GetReg(int index) const { |
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return state->Reg[index]; |
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} |
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/**
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* Set an ARM register |
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* @param index Register index (0-15) |
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* @param value Value to set register to |
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*/ |
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void ARM_DynCom::SetReg(int index, u32 value) { |
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state->Reg[index] = value; |
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} |
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/**
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* Get the current CPSR register |
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* @return Returns the value of the CPSR register |
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*/ |
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u32 ARM_DynCom::GetCPSR() const { |
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return state->Cpsr; |
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} |
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/**
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* Set the current CPSR register |
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* @param cpsr Value to set CPSR to |
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*/ |
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void ARM_DynCom::SetCPSR(u32 cpsr) { |
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state->Cpsr = cpsr; |
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} |
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/**
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* Returns the number of clock ticks since the last reset |
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* @return Returns number of clock ticks |
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*/ |
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u64 ARM_DynCom::GetTicks() const { |
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return ticks; |
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} |
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/**
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* Executes the given number of instructions |
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* @param num_instructions Number of instructions to executes |
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*/ |
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void ARM_DynCom::AddTicks(u64 ticks) { |
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this->ticks += ticks; |
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} |
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void ARM_DynCom::ExecuteInstructions(int num_instructions) { |
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state->NumInstrsToExecute = num_instructions; |
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@ -118,11 +88,6 @@ void ARM_DynCom::ExecuteInstructions(int num_instructions) { |
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ticks += InterpreterMainLoop(state.get()); |
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} |
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/**
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* Saves the current CPU context |
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* @param ctx Thread context to save |
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* @todo Do we need to save Reg[15] and NextInstr? |
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*/ |
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void ARM_DynCom::SaveContext(ThreadContext& ctx) { |
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memcpy(ctx.cpu_registers, state->Reg, sizeof(ctx.cpu_registers)); |
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memcpy(ctx.fpu_registers, state->ExtReg, sizeof(ctx.fpu_registers)); |
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@ -139,11 +104,6 @@ void ARM_DynCom::SaveContext(ThreadContext& ctx) { |
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ctx.mode = state->NextInstr; |
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} |
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/**
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* Loads a CPU context |
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* @param ctx Thread context to load |
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* @param Do we need to load Reg[15] and NextInstr? |
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*/ |
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void ARM_DynCom::LoadContext(const ThreadContext& ctx) { |
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memcpy(state->Reg, ctx.cpu_registers, sizeof(ctx.cpu_registers)); |
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memcpy(state->ExtReg, ctx.fpu_registers, sizeof(ctx.fpu_registers)); |
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@ -160,7 +120,6 @@ void ARM_DynCom::LoadContext(const ThreadContext& ctx) { |
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state->NextInstr = ctx.mode; |
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} |
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/// Prepare core for thread reschedule (if needed to correctly handle state)
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void ARM_DynCom::PrepareReschedule() { |
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state->NumInstrsToExecute = 0; |
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} |