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@ -249,6 +249,7 @@ bool InterpreterVisitor::LDR_lit_fpsimd(Imm<2> opc, Imm<19> imm19, Vec Vt) { |
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return false; |
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return false; |
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} |
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} |
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// Size in bytes
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const u64 size = 4 << opc.ZeroExtend(); |
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const u64 size = 4 << opc.ZeroExtend(); |
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const u64 offset = imm19.SignExtend<u64>() << 2; |
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const u64 offset = imm19.SignExtend<u64>() << 2; |
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const u64 address = this->GetPc() + offset; |
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const u64 address = this->GetPc() + offset; |
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@ -530,7 +531,7 @@ bool InterpreterVisitor::SIMDImmediate(bool wback, bool postindex, size_t scale, |
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} |
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} |
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case MemOp::Load: { |
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case MemOp::Load: { |
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u128 data{}; |
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u128 data{}; |
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m_memory.ReadBlock(address, &data, datasize); |
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m_memory.ReadBlock(address, &data, datasize / 8); |
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this->SetVec(Vt, data); |
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this->SetVec(Vt, data); |
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break; |
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break; |
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} |
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} |
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