bunnei
11 years ago
23 changed files with 320 additions and 415 deletions
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3src/citra_qt/debugger/disassembler.cpp
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7src/core/CMakeLists.txt
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13src/core/arm/dyncom/arm_dyncom.cpp
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2src/core/arm/dyncom/arm_dyncom.h
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4src/core/arm/dyncom/arm_dyncom_dec.cpp
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4src/core/arm/dyncom/arm_dyncom_dec.h
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12src/core/arm/dyncom/arm_dyncom_interpreter.cpp
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2src/core/arm/dyncom/arm_dyncom_interpreter.h
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2src/core/arm/dyncom/arm_dyncom_run.cpp
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2src/core/arm/dyncom/arm_dyncom_run.h
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23src/core/arm/dyncom/arm_dyncom_thumb.cpp
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2src/core/arm/dyncom/arm_dyncom_thumb.h
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318src/core/arm/skyeye_common/armdefs.h
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34src/core/arm/skyeye_common/arminit.cpp
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3src/core/arm/skyeye_common/armmmu.h
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215src/core/arm/skyeye_common/armstate.h
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9src/core/arm/skyeye_common/armsupp.cpp
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40src/core/arm/skyeye_common/armsupp.h
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12src/core/arm/skyeye_common/vfp/vfp.cpp
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10src/core/arm/skyeye_common/vfp/vfp.h
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4src/core/arm/skyeye_common/vfp/vfp_helper.h
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12src/core/arm/skyeye_common/vfp/vfpdouble.cpp
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2src/core/hle/kernel/thread.cpp
@ -1,318 +0,0 @@ |
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/* armdefs.h -- ARMulator common definitions: ARM6 Instruction Emulator. |
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Copyright (C) 1994 Advanced RISC Machines Ltd. |
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This program is free software; you can redistribute it and/or modify |
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it under the terms of the GNU General Public License as published by |
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the Free Software Foundation; either version 2 of the License, or |
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(at your option) any later version. |
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This program is distributed in the hope that it will be useful, |
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but WITHOUT ANY WARRANTY; without even the implied warranty of |
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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GNU General Public License for more details. |
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|
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You should have received a copy of the GNU General Public License |
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along with this program; if not, write to the Free Software |
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ |
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#pragma once |
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#include <unordered_map> |
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#include "common/common_types.h" |
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#include "core/arm/skyeye_common/arm_regformat.h" |
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#define BITS(s, a, b) ((s << ((sizeof(s) * 8 - 1) - b)) >> (sizeof(s) * 8 - b + a - 1)) |
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#define BIT(s, n) ((s >> (n)) & 1) |
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// Signal levels |
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enum { |
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LOW = 0, |
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HIGH = 1, |
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LOWHIGH = 1, |
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HIGHLOW = 2 |
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}; |
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// Cache types |
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enum { |
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NONCACHE = 0, |
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DATACACHE = 1, |
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INSTCACHE = 2, |
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}; |
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// Abort models |
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enum { |
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ABORT_BASE_RESTORED = 0, |
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ABORT_EARLY = 1, |
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ABORT_BASE_UPDATED = 2 |
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}; |
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#define POS(i) ( (~(i)) >> 31 ) |
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#define NEG(i) ( (i) >> 31 ) |
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typedef u64 ARMdword; // must be 64 bits wide |
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typedef u32 ARMword; // must be 32 bits wide |
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typedef u16 ARMhword; // must be 16 bits wide |
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typedef u8 ARMbyte; // must be 8 bits wide |
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#define VFP_REG_NUM 64 |
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struct ARMul_State |
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{ |
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ARMword Emulate; // To start and stop emulation |
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// Order of the following register should not be modified |
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ARMword Reg[16]; // The current register file |
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ARMword Cpsr; // The current PSR |
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ARMword Spsr_copy; |
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ARMword phys_pc; |
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ARMword Reg_usr[2]; |
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ARMword Reg_svc[2]; // R13_SVC R14_SVC |
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ARMword Reg_abort[2]; // R13_ABORT R14_ABORT |
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ARMword Reg_undef[2]; // R13 UNDEF R14 UNDEF |
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ARMword Reg_irq[2]; // R13_IRQ R14_IRQ |
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ARMword Reg_firq[7]; // R8---R14 FIRQ |
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ARMword Spsr[7]; // The exception psr's |
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ARMword Mode; // The current mode |
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ARMword Bank; // The current register bank |
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ARMword exclusive_tag; // The address for which the local monitor is in exclusive access mode |
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ARMword exclusive_state; |
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ARMword exclusive_result; |
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ARMword CP15[CP15_REGISTER_COUNT]; |
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// FPSID, FPSCR, and FPEXC |
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ARMword VFP[VFP_SYSTEM_REGISTER_COUNT]; |
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// VFPv2 and VFPv3-D16 has 16 doubleword registers (D0-D16 or S0-S31). |
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// VFPv3-D32/ASIMD may have up to 32 doubleword registers (D0-D31), |
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// and only 32 singleword registers are accessible (S0-S31). |
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ARMword ExtReg[VFP_REG_NUM]; |
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/* ---- End of the ordered registers ---- */ |
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ARMword NFlag, ZFlag, CFlag, VFlag, IFFlags; // Dummy flags for speed |
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unsigned int shifter_carry_out; |
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// Add armv6 flags dyf:2010-08-09 |
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ARMword GEFlag, EFlag, AFlag, QFlag; |
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ARMword TFlag; // Thumb state |
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unsigned long long NumInstrs; // The number of instructions executed |
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unsigned NumInstrsToExecute; |
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unsigned NresetSig; // Reset the processor |
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unsigned NfiqSig; |
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unsigned NirqSig; |
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unsigned abortSig; |
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unsigned NtransSig; |
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unsigned bigendSig; |
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unsigned syscallSig; |
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/* 2004-05-09 chy |
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---------------------------------------------------------- |
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read ARM Architecture Reference Manual |
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2.6.5 Data Abort |
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There are three Abort Model in ARM arch. |
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Early Abort Model: used in some ARMv3 and earlier implementations. In this |
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model, base register wirteback occurred for LDC,LDM,STC,STM instructions, and |
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the base register was unchanged for all other instructions. (oldest) |
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Base Restored Abort Model: If a Data Abort occurs in an instruction which |
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specifies base register writeback, the value in the base register is |
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unchanged. (strongarm, xscale) |
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Base Updated Abort Model: If a Data Abort occurs in an instruction which |
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specifies base register writeback, the base register writeback still occurs. |
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(arm720T) |
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read PART B |
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chap2 The System Control Coprocessor CP15 |
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2.4 Register1:control register |
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L(bit 6): in some ARMv3 and earlier implementations, the abort model of the |
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processor could be configured: |
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0=early Abort Model Selected(now obsolete) |
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1=Late Abort Model selceted(same as Base Updated Abort Model) |
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on later processors, this bit reads as 1 and ignores writes. |
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------------------------------------------------------------- |
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So, if lateabtSig=1, then it means Late Abort Model(Base Updated Abort Model) |
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if lateabtSig=0, then it means Base Restored Abort Model |
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*/ |
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unsigned lateabtSig; |
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// For differentiating ARM core emulaiton. |
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bool is_v4; // Are we emulating a v4 architecture (or higher)? |
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bool is_v5; // Are we emulating a v5 architecture? |
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bool is_v5e; // Are we emulating a v5e architecture? |
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bool is_v6; // Are we emulating a v6 architecture? |
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bool is_v7; // Are we emulating a v7 architecture? |
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// ARM_ARM A2-18 |
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// 0 Base Restored Abort Model, 1 the Early Abort Model, 2 Base Updated Abort Model |
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int abort_model; |
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// TODO(bunnei): Move this cache to a better place - it should be per codeset (likely per |
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// process for our purposes), not per ARMul_State (which tracks CPU core state). |
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std::unordered_map<u32, int> instruction_cache; |
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}; |
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/***************************************************************************\ |
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* Types of ARM we know about * |
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\***************************************************************************/ |
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enum { |
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ARM_v4_Prop = 0x01, |
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ARM_v5_Prop = 0x02, |
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ARM_v5e_Prop = 0x04, |
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ARM_v6_Prop = 0x08, |
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ARM_v7_Prop = 0x10, |
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}; |
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/***************************************************************************\ |
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* The hardware vector addresses * |
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\***************************************************************************/ |
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enum { |
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ARMResetV = 0, |
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ARMUndefinedInstrV = 4, |
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ARMSWIV = 8, |
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ARMPrefetchAbortV = 12, |
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ARMDataAbortV = 16, |
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ARMAddrExceptnV = 20, |
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ARMIRQV = 24, |
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ARMFIQV = 28, |
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ARMErrorV = 32, // This is an offset, not an address! |
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ARMul_ResetV = ARMResetV, |
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ARMul_UndefinedInstrV = ARMUndefinedInstrV, |
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ARMul_SWIV = ARMSWIV, |
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ARMul_PrefetchAbortV = ARMPrefetchAbortV, |
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ARMul_DataAbortV = ARMDataAbortV, |
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ARMul_AddrExceptnV = ARMAddrExceptnV, |
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ARMul_IRQV = ARMIRQV, |
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ARMul_FIQV = ARMFIQV |
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}; |
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/***************************************************************************\ |
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* Mode and Bank Constants * |
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\***************************************************************************/ |
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enum PrivilegeMode { |
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USER32MODE = 16, |
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FIQ32MODE = 17, |
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IRQ32MODE = 18, |
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SVC32MODE = 19, |
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ABORT32MODE = 23, |
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UNDEF32MODE = 27, |
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SYSTEM32MODE = 31 |
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}; |
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enum { |
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USERBANK = 0, |
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FIQBANK = 1, |
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IRQBANK = 2, |
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SVCBANK = 3, |
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ABORTBANK = 4, |
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UNDEFBANK = 5, |
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DUMMYBANK = 6, |
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SYSTEMBANK = 7 |
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}; |
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/***************************************************************************\ |
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* Definitions of things in the emulator * |
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\***************************************************************************/ |
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void ARMul_Reset(ARMul_State* state); |
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ARMul_State* ARMul_NewState(ARMul_State* state); |
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/***************************************************************************\ |
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* Definitions of things in the co-processor interface * |
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\***************************************************************************/ |
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enum { |
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ARMul_FIRST = 0, |
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ARMul_TRANSFER = 1, |
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ARMul_BUSY = 2, |
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ARMul_DATA = 3, |
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ARMul_INTERRUPT = 4, |
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ARMul_DONE = 0, |
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ARMul_CANT = 1, |
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ARMul_INC = 3 |
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}; |
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/***************************************************************************\ |
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* Definitions of things in the host environment * |
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\***************************************************************************/ |
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enum ConditionCode { |
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EQ = 0, |
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NE = 1, |
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CS = 2, |
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CC = 3, |
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MI = 4, |
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PL = 5, |
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VS = 6, |
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VC = 7, |
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HI = 8, |
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LS = 9, |
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GE = 10, |
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LT = 11, |
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GT = 12, |
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LE = 13, |
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AL = 14, |
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NV = 15, |
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}; |
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// Flags for use with the APSR. |
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enum : u32 { |
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NBIT = (1U << 31U), |
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ZBIT = (1 << 30), |
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CBIT = (1 << 29), |
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VBIT = (1 << 28), |
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QBIT = (1 << 27), |
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JBIT = (1 << 24), |
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EBIT = (1 << 9), |
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ABIT = (1 << 8), |
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IBIT = (1 << 7), |
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FBIT = (1 << 6), |
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TBIT = (1 << 5), |
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// Masks for groups of bits in the APSR. |
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MODEBITS = 0x1F, |
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INTBITS = 0x1C0, |
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}; |
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// Values for Emulate. |
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enum { |
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STOP = 0, // Stop |
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CHANGEMODE = 1, // Change mode |
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ONCE = 2, // Execute just one iteration |
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RUN = 3 // Continuous execution |
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}; |
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bool AddOverflow(ARMword, ARMword, ARMword); |
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bool SubOverflow(ARMword, ARMword, ARMword); |
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void ARMul_SelectProcessor(ARMul_State*, unsigned); |
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u32 AddWithCarry(u32, u32, u32, bool*, bool*); |
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bool ARMul_AddOverflowQ(ARMword, ARMword); |
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u8 ARMul_SignedSaturatedAdd8(u8, u8); |
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u8 ARMul_SignedSaturatedSub8(u8, u8); |
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u16 ARMul_SignedSaturatedAdd16(u16, u16); |
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u16 ARMul_SignedSaturatedSub16(u16, u16); |
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u8 ARMul_UnsignedSaturatedAdd8(u8, u8); |
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u16 ARMul_UnsignedSaturatedAdd16(u16, u16); |
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u8 ARMul_UnsignedSaturatedSub8(u8, u8); |
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u16 ARMul_UnsignedSaturatedSub16(u16, u16); |
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u8 ARMul_UnsignedAbsoluteDifference(u8, u8); |
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u32 ARMul_SignedSatQ(s32, u8, bool*); |
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u32 ARMul_UnsignedSatQ(s32, u8, bool*); |
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bool InBigEndianMode(ARMul_State*); |
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bool InAPrivilegedMode(ARMul_State*); |
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u32 ReadCP15Register(ARMul_State* cpu, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2); |
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void WriteCP15Register(ARMul_State* cpu, u32 value, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2); |
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@ -0,0 +1,215 @@ |
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/* armdefs.h -- ARMulator common definitions: ARM6 Instruction Emulator. |
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Copyright (C) 1994 Advanced RISC Machines Ltd. |
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This program is free software; you can redistribute it and/or modify |
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it under the terms of the GNU General Public License as published by |
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the Free Software Foundation; either version 2 of the License, or |
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(at your option) any later version. |
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This program is distributed in the hope that it will be useful, |
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but WITHOUT ANY WARRANTY; without even the implied warranty of |
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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GNU General Public License for more details. |
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|
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You should have received a copy of the GNU General Public License |
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|
along with this program; if not, write to the Free Software |
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ |
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#pragma once |
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#include <unordered_map> |
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#include "common/common_types.h" |
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#include "core/arm/skyeye_common/arm_regformat.h" |
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// Signal levels |
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enum { |
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LOW = 0, |
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HIGH = 1, |
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LOWHIGH = 1, |
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HIGHLOW = 2 |
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}; |
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// Cache types |
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enum { |
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NONCACHE = 0, |
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DATACACHE = 1, |
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INSTCACHE = 2, |
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}; |
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#define VFP_REG_NUM 64 |
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struct ARMul_State |
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{ |
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u32 Emulate; // To start and stop emulation |
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// Order of the following register should not be modified |
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u32 Reg[16]; // The current register file |
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u32 Cpsr; // The current PSR |
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u32 Spsr_copy; |
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u32 phys_pc; |
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u32 Reg_usr[2]; |
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u32 Reg_svc[2]; // R13_SVC R14_SVC |
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u32 Reg_abort[2]; // R13_ABORT R14_ABORT |
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u32 Reg_undef[2]; // R13 UNDEF R14 UNDEF |
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u32 Reg_irq[2]; // R13_IRQ R14_IRQ |
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u32 Reg_firq[7]; // R8---R14 FIRQ |
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u32 Spsr[7]; // The exception psr's |
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u32 Mode; // The current mode |
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u32 Bank; // The current register bank |
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u32 exclusive_tag; // The address for which the local monitor is in exclusive access mode |
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u32 exclusive_state; |
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u32 exclusive_result; |
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u32 CP15[CP15_REGISTER_COUNT]; |
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// FPSID, FPSCR, and FPEXC |
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u32 VFP[VFP_SYSTEM_REGISTER_COUNT]; |
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// VFPv2 and VFPv3-D16 has 16 doubleword registers (D0-D16 or S0-S31). |
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// VFPv3-D32/ASIMD may have up to 32 doubleword registers (D0-D31), |
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// and only 32 singleword registers are accessible (S0-S31). |
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u32 ExtReg[VFP_REG_NUM]; |
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/* ---- End of the ordered registers ---- */ |
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u32 NFlag, ZFlag, CFlag, VFlag, IFFlags; // Dummy flags for speed |
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unsigned int shifter_carry_out; |
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// Add armv6 flags dyf:2010-08-09 |
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u32 GEFlag, EFlag, AFlag, QFlag; |
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u32 TFlag; // Thumb state |
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unsigned long long NumInstrs; // The number of instructions executed |
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unsigned NumInstrsToExecute; |
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unsigned NresetSig; // Reset the processor |
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unsigned NfiqSig; |
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unsigned NirqSig; |
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unsigned abortSig; |
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unsigned NtransSig; |
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unsigned bigendSig; |
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unsigned syscallSig; |
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||||
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// TODO(bunnei): Move this cache to a better place - it should be per codeset (likely per |
||||
|
// process for our purposes), not per ARMul_State (which tracks CPU core state). |
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|
std::unordered_map<u32, int> instruction_cache; |
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}; |
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||||
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/***************************************************************************\ |
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* The hardware vector addresses * |
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\***************************************************************************/ |
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|
|
||||
|
enum { |
||||
|
ARMResetV = 0, |
||||
|
ARMUndefinedInstrV = 4, |
||||
|
ARMSWIV = 8, |
||||
|
ARMPrefetchAbortV = 12, |
||||
|
ARMDataAbortV = 16, |
||||
|
ARMAddrExceptnV = 20, |
||||
|
ARMIRQV = 24, |
||||
|
ARMFIQV = 28, |
||||
|
ARMErrorV = 32, // This is an offset, not an address! |
||||
|
|
||||
|
ARMul_ResetV = ARMResetV, |
||||
|
ARMul_UndefinedInstrV = ARMUndefinedInstrV, |
||||
|
ARMul_SWIV = ARMSWIV, |
||||
|
ARMul_PrefetchAbortV = ARMPrefetchAbortV, |
||||
|
ARMul_DataAbortV = ARMDataAbortV, |
||||
|
ARMul_AddrExceptnV = ARMAddrExceptnV, |
||||
|
ARMul_IRQV = ARMIRQV, |
||||
|
ARMul_FIQV = ARMFIQV |
||||
|
}; |
||||
|
|
||||
|
/***************************************************************************\ |
||||
|
* Mode and Bank Constants * |
||||
|
\***************************************************************************/ |
||||
|
|
||||
|
enum PrivilegeMode { |
||||
|
USER32MODE = 16, |
||||
|
FIQ32MODE = 17, |
||||
|
IRQ32MODE = 18, |
||||
|
SVC32MODE = 19, |
||||
|
ABORT32MODE = 23, |
||||
|
UNDEF32MODE = 27, |
||||
|
SYSTEM32MODE = 31 |
||||
|
}; |
||||
|
|
||||
|
enum { |
||||
|
USERBANK = 0, |
||||
|
FIQBANK = 1, |
||||
|
IRQBANK = 2, |
||||
|
SVCBANK = 3, |
||||
|
ABORTBANK = 4, |
||||
|
UNDEFBANK = 5, |
||||
|
DUMMYBANK = 6, |
||||
|
SYSTEMBANK = 7 |
||||
|
}; |
||||
|
|
||||
|
/***************************************************************************\ |
||||
|
* Definitions of things in the emulator * |
||||
|
\***************************************************************************/ |
||||
|
void ARMul_Reset(ARMul_State* state); |
||||
|
|
||||
|
/***************************************************************************\ |
||||
|
* Definitions of things in the co-processor interface * |
||||
|
\***************************************************************************/ |
||||
|
|
||||
|
enum { |
||||
|
ARMul_FIRST = 0, |
||||
|
ARMul_TRANSFER = 1, |
||||
|
ARMul_BUSY = 2, |
||||
|
ARMul_DATA = 3, |
||||
|
ARMul_INTERRUPT = 4, |
||||
|
ARMul_DONE = 0, |
||||
|
ARMul_CANT = 1, |
||||
|
ARMul_INC = 3 |
||||
|
}; |
||||
|
|
||||
|
/***************************************************************************\ |
||||
|
* Definitions of things in the host environment * |
||||
|
\***************************************************************************/ |
||||
|
|
||||
|
enum ConditionCode { |
||||
|
EQ = 0, |
||||
|
NE = 1, |
||||
|
CS = 2, |
||||
|
CC = 3, |
||||
|
MI = 4, |
||||
|
PL = 5, |
||||
|
VS = 6, |
||||
|
VC = 7, |
||||
|
HI = 8, |
||||
|
LS = 9, |
||||
|
GE = 10, |
||||
|
LT = 11, |
||||
|
GT = 12, |
||||
|
LE = 13, |
||||
|
AL = 14, |
||||
|
NV = 15, |
||||
|
}; |
||||
|
|
||||
|
// Flags for use with the APSR. |
||||
|
enum : u32 { |
||||
|
NBIT = (1U << 31U), |
||||
|
ZBIT = (1 << 30), |
||||
|
CBIT = (1 << 29), |
||||
|
VBIT = (1 << 28), |
||||
|
QBIT = (1 << 27), |
||||
|
JBIT = (1 << 24), |
||||
|
EBIT = (1 << 9), |
||||
|
ABIT = (1 << 8), |
||||
|
IBIT = (1 << 7), |
||||
|
FBIT = (1 << 6), |
||||
|
TBIT = (1 << 5), |
||||
|
|
||||
|
// Masks for groups of bits in the APSR. |
||||
|
MODEBITS = 0x1F, |
||||
|
INTBITS = 0x1C0, |
||||
|
}; |
||||
|
|
||||
|
// Values for Emulate. |
||||
|
enum { |
||||
|
STOP = 0, // Stop |
||||
|
CHANGEMODE = 1, // Change mode |
||||
|
ONCE = 2, // Execute just one iteration |
||||
|
RUN = 3 // Continuous execution |
||||
|
}; |
||||
@ -0,0 +1,40 @@ |
|||||
|
// Copyright 2014 Citra Emulator Project |
||||
|
// Licensed under GPLv2 or any later version |
||||
|
// Refer to the license.txt file included. |
||||
|
|
||||
|
#pragma once |
||||
|
|
||||
|
#include "common/common_types.h" |
||||
|
|
||||
|
struct ARMul_State; |
||||
|
|
||||
|
#define BITS(s, a, b) ((s << ((sizeof(s) * 8 - 1) - b)) >> (sizeof(s) * 8 - b + a - 1)) |
||||
|
#define BIT(s, n) ((s >> (n)) & 1) |
||||
|
|
||||
|
#define POS(i) ( (~(i)) >> 31 ) |
||||
|
#define NEG(i) ( (i) >> 31 ) |
||||
|
|
||||
|
bool AddOverflow(u32, u32, u32); |
||||
|
bool SubOverflow(u32, u32, u32); |
||||
|
|
||||
|
u32 AddWithCarry(u32, u32, u32, bool*, bool*); |
||||
|
bool ARMul_AddOverflowQ(u32, u32); |
||||
|
|
||||
|
u8 ARMul_SignedSaturatedAdd8(u8, u8); |
||||
|
u8 ARMul_SignedSaturatedSub8(u8, u8); |
||||
|
u16 ARMul_SignedSaturatedAdd16(u16, u16); |
||||
|
u16 ARMul_SignedSaturatedSub16(u16, u16); |
||||
|
|
||||
|
u8 ARMul_UnsignedSaturatedAdd8(u8, u8); |
||||
|
u16 ARMul_UnsignedSaturatedAdd16(u16, u16); |
||||
|
u8 ARMul_UnsignedSaturatedSub8(u8, u8); |
||||
|
u16 ARMul_UnsignedSaturatedSub16(u16, u16); |
||||
|
u8 ARMul_UnsignedAbsoluteDifference(u8, u8); |
||||
|
u32 ARMul_SignedSatQ(s32, u8, bool*); |
||||
|
u32 ARMul_UnsignedSatQ(s32, u8, bool*); |
||||
|
|
||||
|
bool InBigEndianMode(ARMul_State*); |
||||
|
bool InAPrivilegedMode(ARMul_State*); |
||||
|
|
||||
|
u32 ReadCP15Register(ARMul_State* cpu, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2); |
||||
|
void WriteCP15Register(ARMul_State* cpu, u32 value, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2); |
||||
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