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@ -289,7 +289,7 @@ struct Regs { |
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TevStageConfig tev_stage4; |
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INSERT_PADDING_WORDS(0x3); |
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TevStageConfig tev_stage5; |
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INSERT_PADDING_WORDS(0x13); |
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INSERT_PADDING_WORDS(0x3); |
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const std::array<Regs::TevStageConfig,6> GetTevStages() const { |
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return { tev_stage0, tev_stage1, |
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@ -297,6 +297,59 @@ struct Regs { |
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tev_stage4, tev_stage5 }; |
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}; |
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struct { |
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enum DepthFunc : u32 { |
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Always = 1, |
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GreaterThan = 6, |
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}; |
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union { |
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// If false, logic blending is used |
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BitField<8, 1, u32> alphablend_enable; |
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}; |
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union { |
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enum BlendEquation : u32 { |
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Add = 0, |
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}; |
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enum BlendFactor : u32 { |
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Zero = 0, |
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One = 1, |
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SourceAlpha = 6, |
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OneMinusSourceAlpha = 7, |
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}; |
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BitField< 0, 8, BlendEquation> blend_equation_rgb; |
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BitField< 8, 8, BlendEquation> blend_equation_a; |
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BitField<16, 4, BlendFactor> factor_source_rgb; |
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BitField<20, 4, BlendFactor> factor_dest_rgb; |
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BitField<24, 4, BlendFactor> factor_source_a; |
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BitField<28, 4, BlendFactor> factor_dest_a; |
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} alpha_blending; |
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union { |
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enum Op { |
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Set = 4, |
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}; |
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BitField<0, 4, Op> op; |
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} logic_op; |
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INSERT_PADDING_WORDS(0x4); |
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union { |
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BitField< 0, 1, u32> depth_test_enable; |
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BitField< 4, 3, DepthFunc> depth_test_func; |
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BitField<12, 1, u32> depth_write_enable; |
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}; |
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INSERT_PADDING_WORDS(0x8); |
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} output_merger; |
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struct { |
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enum ColorFormat : u32 { |
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RGBA8 = 0, |
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@ -623,6 +676,7 @@ struct Regs { |
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ADD_FIELD(tev_stage3); |
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ADD_FIELD(tev_stage4); |
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ADD_FIELD(tev_stage5); |
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ADD_FIELD(output_merger); |
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ADD_FIELD(framebuffer); |
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ADD_FIELD(vertex_attributes); |
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ADD_FIELD(index_array); |
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@ -695,6 +749,7 @@ ASSERT_REG_POSITION(tev_stage2, 0xd0); |
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ASSERT_REG_POSITION(tev_stage3, 0xd8); |
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ASSERT_REG_POSITION(tev_stage4, 0xf0); |
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ASSERT_REG_POSITION(tev_stage5, 0xf8); |
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ASSERT_REG_POSITION(output_merger, 0x100); |
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ASSERT_REG_POSITION(framebuffer, 0x110); |
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ASSERT_REG_POSITION(vertex_attributes, 0x200); |
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ASSERT_REG_POSITION(index_array, 0x227); |
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