From 3413fbd9da657a9b92398256ffe3bf3b4ac005ee Mon Sep 17 00:00:00 2001 From: Caio Oliveira Date: Mon, 22 Dec 2025 02:58:40 +0100 Subject: [PATCH] [FIXUP] Partially revert "[NCE] Fix cache invalidation and signal interrupt race condition (#3063)" (#3190) * this fixes Jamboree and SSB This reverts commit e3c942b2092761c1f812f1eff086f437b843341a. Reviewed-on: https://git.eden-emu.dev/eden-emu/eden/pulls/3190 Reviewed-by: Maufeat Reviewed-by: MaranBr Co-authored-by: Caio Oliveira Co-committed-by: Caio Oliveira --- src/core/arm/nce/arm_nce.cpp | 17 ++--------------- 1 file changed, 2 insertions(+), 15 deletions(-) diff --git a/src/core/arm/nce/arm_nce.cpp b/src/core/arm/nce/arm_nce.cpp index dae3983a17..cc1e016ba1 100644 --- a/src/core/arm/nce/arm_nce.cpp +++ b/src/core/arm/nce/arm_nce.cpp @@ -391,28 +391,15 @@ const std::size_t CACHE_PAGE_SIZE = 4096; void ArmNce::ClearInstructionCache() { #ifdef __aarch64__ - // Use IC IALLU to actually invalidate L1 instruction cache + // Ensure all previous memory operations complete asm volatile("dsb ish\n" - "ic iallu\n" "dsb ish\n" "isb" ::: "memory"); #endif } void ArmNce::InvalidateCacheRange(u64 addr, std::size_t size) { -#ifdef ARCHITECTURE_arm64 - // Invalidate instruction cache for specific range instead of full flush - constexpr u64 cache_line_size = 64; - const u64 aligned_addr = addr & ~(cache_line_size - 1); - const u64 end_addr = (addr + size + cache_line_size - 1) & ~(cache_line_size - 1); - - asm volatile("dsb ish" ::: "memory"); - for (u64 i = aligned_addr; i < end_addr; i += cache_line_size) { - asm volatile("ic ivau, %0" :: "r"(i) : "memory"); - } - asm volatile("dsb ish\n" - "isb" ::: "memory"); -#endif + this->ClearInstructionCache(); } } // namespace Core