From 1cf0e71fdb21b7601d65249121b8af9786998f33 Mon Sep 17 00:00:00 2001
From: lizzie <lizzie@eden-emu.dev>
Date: Tue, 4 Nov 2025 03:41:22 +0000
Subject: [PATCH] "A64: ADD" passes (except on PC check)

Signed-off-by: lizzie <lizzie@eden-emu.dev>
---
 .../dynarmic/backend/ppc64/a64_interface.cpp  |  4 +++
 .../src/dynarmic/backend/ppc64/emit_ppc64.cpp |  7 ++++--
 .../dynarmic/backend/ppc64/emit_ppc64_a32.cpp |  4 +--
 .../dynarmic/backend/ppc64/emit_ppc64_a64.cpp | 25 +++++++++++++++----
 4 files changed, 31 insertions(+), 9 deletions(-)

diff --git a/src/dynarmic/src/dynarmic/backend/ppc64/a64_interface.cpp b/src/dynarmic/src/dynarmic/backend/ppc64/a64_interface.cpp
index 2e2b3421b6..0490792546 100644
--- a/src/dynarmic/src/dynarmic/backend/ppc64/a64_interface.cpp
+++ b/src/dynarmic/src/dynarmic/backend/ppc64/a64_interface.cpp
@@ -34,6 +34,10 @@ CodePtr A64AddressSpace::GetOrEmit(IR::LocationDescriptor desc) {
     };
     IR::Block ir_block = A64::Translate(A64::LocationDescriptor{desc}, get_code, {conf.define_unpredictable_behaviour, conf.wall_clock_cntpct});
     Optimization::Optimize(ir_block, conf, {});
+
+    fmt::print("IR:\n");
+    fmt::print("{}\n", IR::DumpBlock(ir_block));
+
     const EmittedBlockInfo block_info = Emit(std::move(ir_block));
 
     block_infos.insert_or_assign(desc.Value(), block_info);
diff --git a/src/dynarmic/src/dynarmic/backend/ppc64/emit_ppc64.cpp b/src/dynarmic/src/dynarmic/backend/ppc64/emit_ppc64.cpp
index 6109d4c3a9..6a7cd85a0e 100644
--- a/src/dynarmic/src/dynarmic/backend/ppc64/emit_ppc64.cpp
+++ b/src/dynarmic/src/dynarmic/backend/ppc64/emit_ppc64.cpp
@@ -23,8 +23,11 @@ template<>
 void EmitIR<IR::Opcode::Void>(powah::Context&, EmitContext&, IR::Inst*) {}
 
 template<>
-void EmitIR<IR::Opcode::Identity>(powah::Context&, EmitContext& ctx, IR::Inst* inst) {
-    ASSERT(false && "unimp");
+void EmitIR<IR::Opcode::Identity>(powah::Context& code, EmitContext& ctx, IR::Inst* inst) {
+    powah::GPR const result = ctx.reg_alloc.ScratchGpr();
+    powah::GPR const source = ctx.reg_alloc.UseGpr(inst->GetArg(0));
+    code.MR(result, source);
+    ctx.reg_alloc.DefineValue(inst, result);
 }
 
 template<>
diff --git a/src/dynarmic/src/dynarmic/backend/ppc64/emit_ppc64_a32.cpp b/src/dynarmic/src/dynarmic/backend/ppc64/emit_ppc64_a32.cpp
index 2200df3c8c..e577debe1e 100644
--- a/src/dynarmic/src/dynarmic/backend/ppc64/emit_ppc64_a32.cpp
+++ b/src/dynarmic/src/dynarmic/backend/ppc64/emit_ppc64_a32.cpp
@@ -80,7 +80,7 @@ void EmitIR<IR::Opcode::A32GetRegister>(powah::Context& code, EmitContext& ctx,
     if (inst->GetArg(0).GetType() == IR::Type::A32Reg) {
         powah::GPR const result = ctx.reg_alloc.ScratchGpr();
         code.ADDI(result, PPC64::RJIT, A32::RegNumber(inst->GetArg(0).GetA32RegRef()) * sizeof(u32));
-        code.LD(result, result, offsetof(A32JitState, regs));
+        code.LWZ(result, result, offsetof(A32JitState, regs));
         ctx.reg_alloc.DefineValue(inst, result);
     } else {
         ASSERT(false && "unimp");
@@ -108,7 +108,7 @@ void EmitIR<IR::Opcode::A32SetRegister>(powah::Context& code, EmitContext& ctx,
     if (inst->GetArg(0).GetType() == IR::Type::A32Reg) {
         powah::GPR const addr = ctx.reg_alloc.ScratchGpr();
         code.ADDI(addr, PPC64::RJIT, A32::RegNumber(inst->GetArg(0).GetA32RegRef()) * sizeof(u32));
-        code.STD(value, addr, offsetof(A32JitState, regs));
+        code.STW(value, addr, offsetof(A32JitState, regs));
     } else {
         ASSERT(false && "unimp");
     }
diff --git a/src/dynarmic/src/dynarmic/backend/ppc64/emit_ppc64_a64.cpp b/src/dynarmic/src/dynarmic/backend/ppc64/emit_ppc64_a64.cpp
index d74baa8252..9a2a7fd4e3 100644
--- a/src/dynarmic/src/dynarmic/backend/ppc64/emit_ppc64_a64.cpp
+++ b/src/dynarmic/src/dynarmic/backend/ppc64/emit_ppc64_a64.cpp
@@ -4,7 +4,8 @@
 #include <powah_emit.hpp>
 #include <fmt/ostream.h>
 
-#include "dynarmic/backend/ppc64/a32_core.h"
+#include "dynarmic/frontend/A64/a64_types.h"
+#include "dynarmic/backend/ppc64/a64_core.h"
 #include "dynarmic/backend/ppc64/abi.h"
 #include "dynarmic/backend/ppc64/emit_context.h"
 #include "dynarmic/backend/ppc64/emit_ppc64.h"
@@ -46,8 +47,15 @@ void EmitIR<IR::Opcode::A64GetW>(powah::Context&, EmitContext&, IR::Inst*) {
 }
 
 template<>
-void EmitIR<IR::Opcode::A64GetX>(powah::Context&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "unimp");
+void EmitIR<IR::Opcode::A64GetX>(powah::Context& code, EmitContext& ctx, IR::Inst* inst) {
+    if (inst->GetArg(0).GetType() == IR::Type::A64Reg) {
+        powah::GPR const result = ctx.reg_alloc.ScratchGpr();
+        code.ADDI(result, PPC64::RJIT, A64::RegNumber(inst->GetArg(0).GetA64RegRef()) * sizeof(u64));
+        code.LD(result, result, offsetof(A64JitState, regs));
+        ctx.reg_alloc.DefineValue(inst, result);
+    } else {
+        ASSERT(false && "unimp");
+    }
 }
 
 template<>
@@ -86,8 +94,15 @@ void EmitIR<IR::Opcode::A64SetW>(powah::Context&, EmitContext&, IR::Inst*) {
 }
 
 template<>
-void EmitIR<IR::Opcode::A64SetX>(powah::Context&, EmitContext&, IR::Inst*) {
-    ASSERT(false && "unimp");
+void EmitIR<IR::Opcode::A64SetX>(powah::Context& code, EmitContext& ctx, IR::Inst* inst) {
+    powah::GPR const value = ctx.reg_alloc.UseGpr(inst->GetArg(1));
+    if (inst->GetArg(0).GetType() == IR::Type::A64Reg) {
+        powah::GPR const addr = ctx.reg_alloc.ScratchGpr();
+        code.ADDI(addr, PPC64::RJIT, A64::RegNumber(inst->GetArg(0).GetA64RegRef()) * sizeof(u64));
+        code.STD(value, addr, offsetof(A64JitState, regs));
+    } else {
+        ASSERT(false && "unimp");
+    }
 }
 
 template<>