[nce] more apple fixes

Signed-off-by: lizzie <lizzie@eden-emu.dev>

src/core/arm/nce/arm_nce.cpp

@@ -86,7 +86,7 @@ void ArmNce::SaveGuestContext(GuestContext* guest_ctx, void* raw_context) {
     // Restore host callee-saved registers.
     std::memcpy(&CTX_X(19), guest_ctx->host_ctx.host_saved_regs.data(),
                 sizeof(guest_ctx->host_ctx.host_saved_regs));
-    std::memcpy(&fpctx->vregs[8], guest_ctx->host_ctx.host_saved_vregs.data(),
+    std::memcpy(&CTX_Q(8), guest_ctx->host_ctx.host_saved_vregs.data(),
                 sizeof(guest_ctx->host_ctx.host_saved_vregs));
     // Return from the call on exit by setting pc to x30.
     CTX_PC = guest_ctx->host_ctx.host_saved_regs[11];
@@ -125,17 +125,13 @@ bool ArmNce::HandleFailedGuestFault(GuestContext* guest_ctx, void* raw_info, voi
 }
 
 bool ArmNce::HandleGuestAlignmentFault(GuestContext* guest_ctx, void* raw_info, void* raw_context) {
-    auto& host_ctx = static_cast<ucontext_t*>(raw_context)->uc_mcontext;
-    auto* fpctx = GetFloatingPointState(host_ctx);
+    CTX_DECLARE(raw_context);
     auto& memory = guest_ctx->system->ApplicationMemory();
-
     // Match and execute an instruction.
-    auto next_pc = MatchAndExecuteOneInstruction(memory, &host_ctx);
-    if (next_pc) {
+    if (auto next_pc = MatchAndExecuteOneInstruction(memory, raw_context); next_pc) {
         host_ctx.pc = *next_pc;
         return true;
     }
-
     // We couldn't handle the access.
     return HandleFailedGuestFault(guest_ctx, raw_info, raw_context);
 }

src/core/arm/nce/arm_nce.s

@@ -9,9 +9,11 @@
 
 
 /* static HaltReason Core::ArmNce::ReturnToRunCodeByTrampoline(void* tpidr, Core::GuestContext* ctx, u64 trampoline_addr) */
+#ifndef __APPLE__
 .section    .text._ZN4Core6ArmNce27ReturnToRunCodeByTrampolineEPvPNS_12GuestContextEm, "ax", %progbits
-.global     _ZN4Core6ArmNce27ReturnToRunCodeByTrampolineEPvPNS_12GuestContextEm
 .type       _ZN4Core6ArmNce27ReturnToRunCodeByTrampolineEPvPNS_12GuestContextEm, %function
+#endif
+.global     _ZN4Core6ArmNce27ReturnToRunCodeByTrampolineEPvPNS_12GuestContextEm
 _ZN4Core6ArmNce27ReturnToRunCodeByTrampolineEPvPNS_12GuestContextEm:
     /* Back up host sp to x3. */
     /* Back up host tpidr_el0 to x4. */
@@ -50,9 +52,11 @@ _ZN4Core6ArmNce27ReturnToRunCodeByTrampolineEPvPNS_12GuestContextEm:
 
 
 /* static HaltReason Core::ArmNce::ReturnToRunCodeByExceptionLevelChange(int tid, void* tpidr) */
+#ifndef __APPLE__
 .section    .text._ZN4Core6ArmNce37ReturnToRunCodeByExceptionLevelChangeEiPv, "ax", %progbits
-.global     _ZN4Core6ArmNce37ReturnToRunCodeByExceptionLevelChangeEiPv
 .type       _ZN4Core6ArmNce37ReturnToRunCodeByExceptionLevelChangeEiPv, %function
+#endif
+.global     _ZN4Core6ArmNce37ReturnToRunCodeByExceptionLevelChangeEiPv
 _ZN4Core6ArmNce37ReturnToRunCodeByExceptionLevelChangeEiPv:
     /* This jumps to the signal handler, which will restore the entire context. */
     /* On entry, x0 = thread id, which is already in the right place. */
@@ -72,9 +76,11 @@ _ZN4Core6ArmNce37ReturnToRunCodeByExceptionLevelChangeEiPv:
 
 
 /* static void Core::ArmNce::ReturnToRunCodeByExceptionLevelChangeSignalHandler(int sig, void* info, void* raw_context) */
+#ifndef __APPLE__
 .section    .text._ZN4Core6ArmNce50ReturnToRunCodeByExceptionLevelChangeSignalHandlerEiPvS1_, "ax", %progbits
-.global     _ZN4Core6ArmNce50ReturnToRunCodeByExceptionLevelChangeSignalHandlerEiPvS1_
 .type       _ZN4Core6ArmNce50ReturnToRunCodeByExceptionLevelChangeSignalHandlerEiPvS1_, %function
+#endif
+.global     _ZN4Core6ArmNce50ReturnToRunCodeByExceptionLevelChangeSignalHandlerEiPvS1_
 _ZN4Core6ArmNce50ReturnToRunCodeByExceptionLevelChangeSignalHandlerEiPvS1_:
     stp     x29, x30, [sp, #-0x10]!
     mov     x29, sp
@@ -100,9 +106,11 @@ _ZN4Core6ArmNce50ReturnToRunCodeByExceptionLevelChangeSignalHandlerEiPvS1_:
 
 
 /* static void Core::ArmNce::BreakFromRunCodeSignalHandler(int sig, void* info, void* raw_context) */
+#ifndef __APPLE__
 .section    .text._ZN4Core6ArmNce29BreakFromRunCodeSignalHandlerEiPvS1_, "ax", %progbits
-.global     _ZN4Core6ArmNce29BreakFromRunCodeSignalHandlerEiPvS1_
 .type       _ZN4Core6ArmNce29BreakFromRunCodeSignalHandlerEiPvS1_, %function
+#endif
+.global     _ZN4Core6ArmNce29BreakFromRunCodeSignalHandlerEiPvS1_
 _ZN4Core6ArmNce29BreakFromRunCodeSignalHandlerEiPvS1_:
     /* Check to see if we have the correct TLS magic. */
     mrs     x8, tpidr_el0
@@ -131,9 +139,11 @@ _ZN4Core6ArmNce29BreakFromRunCodeSignalHandlerEiPvS1_:
 
 
 /* static void Core::ArmNce::GuestAlignmentFaultSignalHandler(int sig, void* info, void* raw_context) */
+#ifndef __APPLE__
 .section    .text._ZN4Core6ArmNce32GuestAlignmentFaultSignalHandlerEiPvS1_, "ax", %progbits
-.global     _ZN4Core6ArmNce32GuestAlignmentFaultSignalHandlerEiPvS1_
 .type       _ZN4Core6ArmNce32GuestAlignmentFaultSignalHandlerEiPvS1_, %function
+#endif
+.global     _ZN4Core6ArmNce32GuestAlignmentFaultSignalHandlerEiPvS1_
 _ZN4Core6ArmNce32GuestAlignmentFaultSignalHandlerEiPvS1_:
     /* Check to see if we have the correct TLS magic. */
     mrs     x8, tpidr_el0
@@ -177,9 +187,11 @@ _ZN4Core6ArmNce32GuestAlignmentFaultSignalHandlerEiPvS1_:
     ret
 
 /* static void Core::ArmNce::GuestAccessFaultSignalHandler(int sig, void* info, void* raw_context) */
+#ifndef __APPLE__
 .section    .text._ZN4Core6ArmNce29GuestAccessFaultSignalHandlerEiPvS1_, "ax", %progbits
-.global     _ZN4Core6ArmNce29GuestAccessFaultSignalHandlerEiPvS1_
 .type       _ZN4Core6ArmNce29GuestAccessFaultSignalHandlerEiPvS1_, %function
+#endif
+.global     _ZN4Core6ArmNce29GuestAccessFaultSignalHandlerEiPvS1_
 _ZN4Core6ArmNce29GuestAccessFaultSignalHandlerEiPvS1_:
     /* Check to see if we have the correct TLS magic. */
     mrs     x8, tpidr_el0
@@ -224,9 +236,11 @@ _ZN4Core6ArmNce29GuestAccessFaultSignalHandlerEiPvS1_:
 
 
 /* static void Core::ArmNce::LockThreadParameters(void* tpidr) */
+#ifndef __APPLE__
 .section    .text._ZN4Core6ArmNce20LockThreadParametersEPv, "ax", %progbits
-.global     _ZN4Core6ArmNce20LockThreadParametersEPv
 .type       _ZN4Core6ArmNce20LockThreadParametersEPv, %function
+#endif
+.global     _ZN4Core6ArmNce20LockThreadParametersEPv
 _ZN4Core6ArmNce20LockThreadParametersEPv:
     /* Offset to lock member. */
     add     x0, x0, #(TpidrEl0Lock)
@@ -252,9 +266,11 @@ _ZN4Core6ArmNce20LockThreadParametersEPv:
 
 
 /* static void Core::ArmNce::UnlockThreadParameters(void* tpidr) */
+#ifndef __APPLE__
 .section    .text._ZN4Core6ArmNce22UnlockThreadParametersEPv, "ax", %progbits
-.global     _ZN4Core6ArmNce22UnlockThreadParametersEPv
 .type       _ZN4Core6ArmNce22UnlockThreadParametersEPv, %function
+#endif
+.global     _ZN4Core6ArmNce22UnlockThreadParametersEPv
 _ZN4Core6ArmNce22UnlockThreadParametersEPv:
     /* Offset to lock member. */
     add     x0, x0, #(TpidrEl0Lock)

src/core/arm/nce/arm_nce_asm_definitions.h

@@ -23,11 +23,6 @@
 #define GuestContextSp 0xF8
 #define GuestContextHostContext 0x320
 
-#define HostContextSpTpidrEl0 0xE0
-#define HostContextTpidrEl0 0xE8
-#define HostContextRegs 0x0
-#define HostContextVregs 0x60
-
 #define TpidrEl0NativeContext 0x10
 #define TpidrEl0Lock 0x18
 #define TpidrEl0TlsMagic 0x20
@@ -35,3 +30,8 @@
 
 #define SpinLockLocked 0
 #define SpinLockUnlocked 1
+
+#define HostContextSpTpidrEl0 0xE0
+#define HostContextTpidrEl0 0xE8
+#define HostContextRegs 0x0
+#define HostContextVregs 0x60

src/core/arm/nce/interpreter_visitor.cpp

@@ -7,6 +7,7 @@
 
 #include <numeric>
 #include "core/arm/nce/interpreter_visitor.h"
+#include "dynarmic/common/context.h"
 
 namespace Core {
 
@@ -761,7 +762,8 @@ bool InterpreterVisitor::LDR_reg_fpsimd(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3
     return this->SIMDOffset(scale, shift, opc_0, Rm, option, Rn, Vt);
 }
 
-std::optional<u64> MatchAndExecuteOneInstruction(Core::Memory::Memory& memory, mcontext_t* context) {
+std::optional<u64> MatchAndExecuteOneInstruction(Core::Memory::Memory& memory, void* raw_context) {
+    CTX_DECLARE(raw_context);
     std::span<u64, 31> regs(reinterpret_cast<u64*>(&CTX_X(0)), 31);
     std::span<u128, 32> vregs(reinterpret_cast<u128*>(&CTX_Q(0)), 32);
     u64& sp = *reinterpret_cast<u64*>(&CTX_SP);

src/core/arm/nce/interpreter_visitor.h

@@ -105,6 +105,6 @@ private:
     const u64& m_pc;
 };
 
-std::optional<u64> MatchAndExecuteOneInstruction(Core::Memory::Memory& memory, mcontext_t* context);
+std::optional<u64> MatchAndExecuteOneInstruction(Core::Memory::Memory& memory, void* raw_context);
 
 } // namespace Core