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@ -22,31 +22,36 @@ |
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void switch_mode(ARMul_State* core, uint32_t mode); |
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void switch_mode(ARMul_State* core, uint32_t mode); |
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/* FIXME, we temporarily think thumb instruction is always 16 bit */ |
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// Note that for the 3DS, a Thumb instruction will only ever be |
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// two bytes in size. Thus we don't need to worry about ThumbEE |
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// or Thumb-2 where instructions can be 4 bytes in length. |
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static inline u32 GET_INST_SIZE(ARMul_State* core) { |
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static inline u32 GET_INST_SIZE(ARMul_State* core) { |
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return core->TFlag? 2 : 4; |
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return core->TFlag? 2 : 4; |
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} |
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} |
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/** |
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/** |
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* @brief Read R15 and forced R15 to wold align, used address calculation |
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* |
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* @param core |
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* @param Rn |
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* |
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* @return |
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*/ |
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static inline addr_t CHECK_READ_REG15_WA(ARMul_State* core, int Rn) { |
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return (Rn == 15)? ((core->Reg[15] & ~0x3) + GET_INST_SIZE(core) * 2) : core->Reg[Rn]; |
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* Checks if the PC is being read, and if so, word-aligns it. |
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* Used with address calculations. |
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* |
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* @param core The ARM CPU state instance. |
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* @param Rn The register being read. |
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* |
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* @return If the PC is being read, then the word-aligned PC value is returned. |
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* If the PC is not being read, then the value stored in the register is returned. |
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*/ |
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static inline u32 CHECK_READ_REG15_WA(ARMul_State* core, int Rn) { |
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return (Rn == 15) ? ((core->Reg[15] & ~0x3) + GET_INST_SIZE(core) * 2) : core->Reg[Rn]; |
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} |
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} |
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/** |
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/** |
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* @brief Read R15, used to data processing with pc |
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* |
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* @param core |
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* @param Rn |
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* |
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* @return |
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*/ |
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* Reads the PC. Used for data processing operations that use the PC. |
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* |
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* @param core The ARM CPU state instance. |
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* @param Rn The register being read. |
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* |
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* @return If the PC is being read, then the incremented PC value is returned. |
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* If the PC is not being read, then the values stored in the register is returned. |
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*/ |
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static inline u32 CHECK_READ_REG15(ARMul_State* core, int Rn) { |
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static inline u32 CHECK_READ_REG15(ARMul_State* core, int Rn) { |
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return (Rn == 15)? ((core->Reg[15] & ~0x1) + GET_INST_SIZE(core) * 2) : core->Reg[Rn]; |
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return (Rn == 15) ? ((core->Reg[15] & ~0x1) + GET_INST_SIZE(core) * 2) : core->Reg[Rn]; |
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} |
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} |