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@ -2125,8 +2125,12 @@ private: |
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case OpCode::Id::IPA: { |
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const auto& attribute = instr.attribute.fmt28; |
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const auto& reg = instr.gpr0; |
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switch (instr.ipa.mode) { |
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case Tegra::Shader::IpaMode::Pass: |
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ASSERT_MSG(instr.ipa.sample_mode == Tegra::Shader::IpaSampleMode::Default, |
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"Unhandled IPA sample mode: {}", |
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static_cast<u32>(instr.ipa.sample_mode.Value())); |
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ASSERT_MSG(instr.ipa.saturate == 0, "IPA saturate not implemented"); |
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switch (instr.ipa.interp_mode) { |
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case Tegra::Shader::IpaInterpMode::Linear: |
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if (stage == Maxwell3D::Regs::ShaderStage::Fragment && |
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attribute.index == Attribute::Index::Position) { |
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switch (attribute.element) { |
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@ -2147,12 +2151,12 @@ private: |
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regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index); |
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} |
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break; |
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case Tegra::Shader::IpaMode::None: |
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case Tegra::Shader::IpaInterpMode::Perspective: |
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regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index); |
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break; |
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default: |
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LOG_CRITICAL(HW_GPU, "Unhandled IPA mode: {}", |
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static_cast<u32>(instr.ipa.mode.Value())); |
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static_cast<u32>(instr.ipa.interp_mode.Value())); |
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UNREACHABLE(); |
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regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index); |
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} |
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